VIBNN: Hardware acceleration of Bayesian neural networks

Ruizhe Cai, Ao Ren, Ning Liu, Caiwen Ding, Luhao Wang, Xuehai Qian, Massoud Pedram, Yanzhi Wang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Scopus citations

Abstract

Bayesian Neural Networks (BNNs) have been proposed to address the problem of model uncertainty in training and inference. By introducing weights associated with conditioned probability distributions, BNNs are capable of resolving the overfitting issue commonly seen in conventional neural networks and allow for small-data training, through the variational inference process. Frequent usage of Gaussian random variables in this process requires a properly optimized Gaussian Random Number Generator (GRNG). The high hardware cost of conventional GRNG makes the hardware implementation of BNNs challenging. In this paper, we propose VIBNN, an FPGA-based hardware accelerator design for variational inference on BNNs. We explore the design space for massive amount of Gaussian variable sampling tasks in BNNs. Specifically, we introduce two high performance Gaussian (pseudo) random number generators: 1) the RAM-based LinearFeedback Gaussian Random NumberGenerator (RLF-GRNG), which is inspired by the properties of binomial distribution and linear feedback logics; and 2) the Bayesian Neural Network-oriented Wallace Gaussian Random Number Generator. To achieve high scalability and efficient memory access, we propose a deep pipelined accelerator architecture with fast execution and good hardware utilization. Experimental results demonstrate that the proposed VIBNN implementations on an FPGA can achieve throughput of 321,543.4 Images/s and energy efficiency upto 52,694.8 Images/J while maintaining similar accuracy as its software counterpart.

Original languageEnglish (US)
Title of host publicationProceedings of the 23rd International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2018
PublisherAssociation for Computing Machinery
Pages476-488
Number of pages13
Volume53
Edition2
ISBN (Electronic)9781450349116
DOIs
StatePublished - Mar 19 2018
Event23rd International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2018 - Williamsburg, United States
Duration: Mar 24 2018Mar 28 2018

Other

Other23rd International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2018
CountryUnited States
CityWilliamsburg
Period3/24/183/28/18

Keywords

  • Bayesian Neural Network
  • FPGA
  • Neural network

ASJC Scopus subject areas

  • Computer Science(all)

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