Variation-aware joint optimization of the supply voltage and sleep transistor size for the 7nm FinFET technology

Engineering

• Joints (Structural Components) 100%
• Supply Voltage 100%
• Energy Engineering 80%
• Nodes 40%
• Optimisation Problem 40%
• Delay Circuits 40%
• Experimental Result 20%
• Optimization Technique 20%
• VLSI Circuits 20%
• Propagation Delay 20%
• Smallest Feature 20%
• Feature Size 20%
• Gate Length 20%

Keyphrases

• Variation-aware 100%
• Sleep Transistor 100%
• Power Gating 50%
• Stand-alone Mode 25%
• Small Feature Size 25%
• Gating Mechanism 25%
• Joint Optimization Problem 25%
• Optimal Supply 25%
• Advanced Technology Node 25%