Variation-aware joint optimization of the supply voltage and sleep transistor size for the 7nm FinFET technology

Qing Xie, Yanzhi Wang, Shuang Chen, Massoud Pedram

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

Power gating is a very effective method in reducing the leakage energy during the standby mode in VLSI circuits at the cost of increased circuit delay. This method has been well studied and widely used for circuits fabricated by using traditional CMOS technology nodes operating at super-threshold supply voltage regime. However, for advanced technology nodes with small feature sizes and low supply voltages, the propagation delay becomes very sensitive to the high process-induced variations. Therefore, this paper first analyzes how the circuit delay depends on the size of the sleep transistor under the process-induced variation for the 7nm gate length FinFET technology. Then a joint optimization problem is formulated to minimize the total energy consumption, while both supply voltage and sleep transistor size are considered as optimization variables. A near-optimal heuristic is presented to solve the optimization problem and determine the energy-optimal supply voltage and sleep transistor size. Experimental results based on HSPICE simulations show that more than 98% energy reduction for applications with relaxed deadline constraints after applying the joint optimization technique, compared to FinFET circuits without using the power gating method.

Original languageEnglish (US)
Title of host publication2014 32nd IEEE International Conference on Computer Design, ICCD 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages380-385
Number of pages6
ISBN (Electronic)9781479964925
DOIs
StatePublished - Dec 3 2014
Event32nd IEEE International Conference on Computer Design, ICCD 2014 - Seoul, Korea, Republic of
Duration: Oct 19 2014Oct 22 2014

Publication series

Name2014 32nd IEEE International Conference on Computer Design, ICCD 2014

Other

Other32nd IEEE International Conference on Computer Design, ICCD 2014
CountryKorea, Republic of
CitySeoul
Period10/19/1410/22/14

Keywords

  • FinFETs
  • line-edge roughness
  • power gating
  • process-induced variation
  • sleep transistor sizing
  • voltage scaling

ASJC Scopus subject areas

  • Computer Graphics and Computer-Aided Design
  • Computer Science Applications

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