Soft-edge flip-flop based pipelines can improve the performance and energy efficiency of circuits operating in the super-threshold (supply voltage) regime by allowing opportunistic time borrowing. The application of this technique to near-threshold regime of operation, however, faces a significant challenge due to large circuit parameter variations that result from manufacturing process imperfections and substrate temperature changes. This paper thus addresses the issue of variability-aware design of the energy-delay optimal linear pipelines that are aimed at operating in both the near-threshold and super-threshold regimes. Precisely, this goal is achieved by deriving the optimal delay line configuration in the soft-edge flip-flops in the near-threshold and the super-threshold operations regimes. The key is to ensure that the same transistor sizes result in effective operation of the delay lines (and hence appropriate settings of the transparency window size) in both operation regimes under the process induced variations. Experimental results demonstrate the efficacy of the proposed solution.