Transistor chaining in static CMOS functional cells of arbitrary planar topology

Bradley S. Carlson, C. Y.Roger Chen, Dikran S. Meliksetian

Research output: Contribution to journalArticlepeer-review

1 Scopus citations


A technique for chaining the transistors in the layouts of static CMOS leaf cells is presented and analyzed. This new method is superior to existing techniques, since it can operate on a more general class of circuits and is very efficient. It is shown that the layout width of a CMOS leaf cell can be significantly reduced (nearly 40% in the average case) by transistor chaining. Moreover, more than half of the switching functions of four variables have optimal CMOS circuit implementations with non-series/parallel topologies. Therefore, the use of nonseries/parallel circuits can have a positive global impact on layout area and performance. The transistor chaining technique presented in this paper produces the optimal solution for 82.5% of the circuits tested, and has linear time complexity.

Original languageEnglish (US)
Pages (from-to)89-114
Number of pages26
JournalDiscrete Applied Mathematics
Issue number1-3
StatePublished - Jan 15 1999

ASJC Scopus subject areas

  • Discrete Mathematics and Combinatorics
  • Applied Mathematics


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