TY - JOUR
T1 - Transistor chaining in static CMOS functional cells of arbitrary planar topology
AU - Carlson, Bradley S.
AU - Chen, C. Y.Roger
AU - Meliksetian, Dikran S.
PY - 1999/1/15
Y1 - 1999/1/15
N2 - A technique for chaining the transistors in the layouts of static CMOS leaf cells is presented and analyzed. This new method is superior to existing techniques, since it can operate on a more general class of circuits and is very efficient. It is shown that the layout width of a CMOS leaf cell can be significantly reduced (nearly 40% in the average case) by transistor chaining. Moreover, more than half of the switching functions of four variables have optimal CMOS circuit implementations with non-series/parallel topologies. Therefore, the use of nonseries/parallel circuits can have a positive global impact on layout area and performance. The transistor chaining technique presented in this paper produces the optimal solution for 82.5% of the circuits tested, and has linear time complexity.
AB - A technique for chaining the transistors in the layouts of static CMOS leaf cells is presented and analyzed. This new method is superior to existing techniques, since it can operate on a more general class of circuits and is very efficient. It is shown that the layout width of a CMOS leaf cell can be significantly reduced (nearly 40% in the average case) by transistor chaining. Moreover, more than half of the switching functions of four variables have optimal CMOS circuit implementations with non-series/parallel topologies. Therefore, the use of nonseries/parallel circuits can have a positive global impact on layout area and performance. The transistor chaining technique presented in this paper produces the optimal solution for 82.5% of the circuits tested, and has linear time complexity.
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U2 - 10.1016/S0166-218X(98)00086-9
DO - 10.1016/S0166-218X(98)00086-9
M3 - Article
AN - SCOPUS:0041705395
SN - 0166-218X
VL - 90
SP - 89
EP - 114
JO - Discrete Applied Mathematics
JF - Discrete Applied Mathematics
IS - 1-3
ER -