Transistor chaining in CMOS leaf cells of planar topology

B. S. Carlson, Chien Yi Roger Chen, D. S. Meliksetian

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

A technique for chaining the transistors in the layouts of static CMOS leaf cells is presented and analyzed. This new method is superior to existing techniques, since it can operate on a more general class of circuits and is very efficient. It is shown that the layout width of a CMOS leaf cell can be significantly reduced (nearly 40% in the average case) by transistor chaining. Moreover, more than half of the switching functions of four variables have optimal CMOS circuit implementations with nonseries/parallel topologies. Therefore, the use of nonseries/parallel circuits can have a positive global impact on layout area and performance. The transistor chaining technique presented in this paper produces the optimal solution for 82% of the circuits tested, and has linear time complexity.

Original languageEnglish (US)
Title of host publicationProceedings of the IEEE Great Lakes Symposium on VLSI
PublisherIEEE Computer Society
Pages194-199
Number of pages6
StatePublished - 1996
Externally publishedYes
EventProceedings of the 1996 6th Great Lakes Symposium on VLSI, GLSVLSI - Ames, IA, USA
Duration: Mar 22 1996Mar 23 1996

Other

OtherProceedings of the 1996 6th Great Lakes Symposium on VLSI, GLSVLSI
CityAmes, IA, USA
Period3/22/963/23/96

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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