Transistor and pin reordering for leakage reduction in CMOS circuits

Jae Woong Chun, Chien Yi Roger Chen

Research output: Contribution to journalArticle

3 Citations (Scopus)

Abstract

Leakage power is currently a critical problem in nanometer-scale CMOS circuit technology. In this paper, a novel reordering method for reducing the overall leakage currents is proposed for CMOS logic gates, including CMOS complex gates. This new method takes into account the subthreshold leakage current (ISUB) and gate leakage current (IG) and includes the often-ignored reverse gate tunneling current (IRG). Additionally, this method considers the interaction between leakage components based on the stacking/non-stacking effect case and different W/L ratios of an on-/off-transistor block in a stack. Thus, unlike existing approaches, the proposed method can generate the best configuration for leakage reduction even in CMOS complex gates, and can be used in combination with other leakage reduction techniques to achieve further improvement.

Original languageEnglish (US)
Pages (from-to)25-34
Number of pages10
JournalMicroelectronics Journal
Volume53
DOIs
StatePublished - Jul 1 2016

Fingerprint

Leakage currents
CMOS
Transistors
leakage
transistors
Networks (circuits)
Logic gates
logic
configurations
interactions

Keywords

  • Gate leakage
  • Leakage power reduction
  • Pin reordering
  • Power state dependency
  • Subthreshold leakage
  • Transistor reordering

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials
  • Surfaces, Coatings and Films
  • Atomic and Molecular Physics, and Optics
  • Condensed Matter Physics

Cite this

Transistor and pin reordering for leakage reduction in CMOS circuits. / Chun, Jae Woong; Chen, Chien Yi Roger.

In: Microelectronics Journal, Vol. 53, 01.07.2016, p. 25-34.

Research output: Contribution to journalArticle

@article{3693affe14434fbab4a79d115d58705e,
title = "Transistor and pin reordering for leakage reduction in CMOS circuits",
abstract = "Leakage power is currently a critical problem in nanometer-scale CMOS circuit technology. In this paper, a novel reordering method for reducing the overall leakage currents is proposed for CMOS logic gates, including CMOS complex gates. This new method takes into account the subthreshold leakage current (ISUB) and gate leakage current (IG) and includes the often-ignored reverse gate tunneling current (IRG). Additionally, this method considers the interaction between leakage components based on the stacking/non-stacking effect case and different W/L ratios of an on-/off-transistor block in a stack. Thus, unlike existing approaches, the proposed method can generate the best configuration for leakage reduction even in CMOS complex gates, and can be used in combination with other leakage reduction techniques to achieve further improvement.",
keywords = "Gate leakage, Leakage power reduction, Pin reordering, Power state dependency, Subthreshold leakage, Transistor reordering",
author = "Chun, {Jae Woong} and Chen, {Chien Yi Roger}",
year = "2016",
month = "7",
day = "1",
doi = "10.1016/j.mejo.2016.04.005",
language = "English (US)",
volume = "53",
pages = "25--34",
journal = "Microelectronics",
issn = "0959-8324",
publisher = "Elsevier",

}

TY - JOUR

T1 - Transistor and pin reordering for leakage reduction in CMOS circuits

AU - Chun, Jae Woong

AU - Chen, Chien Yi Roger

PY - 2016/7/1

Y1 - 2016/7/1

N2 - Leakage power is currently a critical problem in nanometer-scale CMOS circuit technology. In this paper, a novel reordering method for reducing the overall leakage currents is proposed for CMOS logic gates, including CMOS complex gates. This new method takes into account the subthreshold leakage current (ISUB) and gate leakage current (IG) and includes the often-ignored reverse gate tunneling current (IRG). Additionally, this method considers the interaction between leakage components based on the stacking/non-stacking effect case and different W/L ratios of an on-/off-transistor block in a stack. Thus, unlike existing approaches, the proposed method can generate the best configuration for leakage reduction even in CMOS complex gates, and can be used in combination with other leakage reduction techniques to achieve further improvement.

AB - Leakage power is currently a critical problem in nanometer-scale CMOS circuit technology. In this paper, a novel reordering method for reducing the overall leakage currents is proposed for CMOS logic gates, including CMOS complex gates. This new method takes into account the subthreshold leakage current (ISUB) and gate leakage current (IG) and includes the often-ignored reverse gate tunneling current (IRG). Additionally, this method considers the interaction between leakage components based on the stacking/non-stacking effect case and different W/L ratios of an on-/off-transistor block in a stack. Thus, unlike existing approaches, the proposed method can generate the best configuration for leakage reduction even in CMOS complex gates, and can be used in combination with other leakage reduction techniques to achieve further improvement.

KW - Gate leakage

KW - Leakage power reduction

KW - Pin reordering

KW - Power state dependency

KW - Subthreshold leakage

KW - Transistor reordering

UR - http://www.scopus.com/inward/record.url?scp=84964755819&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84964755819&partnerID=8YFLogxK

U2 - 10.1016/j.mejo.2016.04.005

DO - 10.1016/j.mejo.2016.04.005

M3 - Article

AN - SCOPUS:84964755819

VL - 53

SP - 25

EP - 34

JO - Microelectronics

JF - Microelectronics

SN - 0959-8324

ER -