Transistor and pin reordering for leakage reduction in CMOS circuits

Leakage power is currently a critical problem in nanometer-scale CMOS circuit technology. In this paper, a novel reordering method for reducing the overall leakage currents is proposed for CMOS logic gates, including CMOS complex gates. This new method takes into account the subthreshold leakage current (I_SUB) and gate leakage current (I_G) and includes the often-ignored reverse gate tunneling current (I_RG). Additionally, this method considers the interaction between leakage components based on the stacking/non-stacking effect case and different <FOR VERIFICATION-sup/inf>W/L<FOR VERIFICATION-sup/inf> ratios of an on-/off-transistor block in a stack. Thus, unlike existing approaches, the proposed method can generate the best configuration for leakage reduction even in CMOS complex gates, and can be used in combination with other leakage reduction techniques to achieve further improvement.