Towards parallel implementation of associative inference for cogent confabulation

Zhe Li, Qinru Qiu, Mangesh Tamhankar

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

The superb efficiency and noise resilience of human cognizance comes from the extensive highly associative memory. For example, it is easy for human to recognize occluded or incomplete text images based on its context. Associative inference in the neocortex system is a concurrent process. Serial implementation of this concurrent process not only hinders its performance, but also limits the quality of recall. This paper investigates parallel implementation of associative inference using cogent confabulation model, which is a highly cross-dependent and cyclic knowledge network that supports probabilistic inference. By breaking the fixed processing order, which is typical in sequential processing, and introducing randomness generated from the race conditions in parallel processing, we do not only reduce the runtime, but also improve the accuracy. Further improvement can be achieved by scheduling the lexicon processing intermittently, which provides time for the changes to settle down. Using sentence construction as a case study, we demonstrate that the parallel implementation provides up to 93.4% reduction in computation time and 5% improvement in recall accuracy.

Original languageEnglish (US)
Title of host publication2016 IEEE High Performance Extreme Computing Conference, HPEC 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781509035250
DOIs
StatePublished - Nov 28 2016
Event2016 IEEE High Performance Extreme Computing Conference, HPEC 2016 - Waltham, United States
Duration: Sep 13 2016Sep 15 2016

Other

Other2016 IEEE High Performance Extreme Computing Conference, HPEC 2016
CountryUnited States
CityWaltham
Period9/13/169/15/16

Fingerprint

Parallel Implementation
Concurrent
Processing
Probabilistic Inference
Associative Memory
Hazards and race conditions
Resilience
Parallel Processing
Randomness
Scheduling
Dependent
Data storage equipment
Demonstrate
Human
Model

Keywords

  • Cogent Confabulation
  • Multi-Threading
  • Parallel Programming
  • Sentence Completion

ASJC Scopus subject areas

  • Computer Science (miscellaneous)
  • Hardware and Architecture
  • Computational Mathematics

Cite this

Li, Z., Qiu, Q., & Tamhankar, M. (2016). Towards parallel implementation of associative inference for cogent confabulation. In 2016 IEEE High Performance Extreme Computing Conference, HPEC 2016 [7761623] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/HPEC.2016.7761623

Towards parallel implementation of associative inference for cogent confabulation. / Li, Zhe; Qiu, Qinru; Tamhankar, Mangesh.

2016 IEEE High Performance Extreme Computing Conference, HPEC 2016. Institute of Electrical and Electronics Engineers Inc., 2016. 7761623.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Li, Z, Qiu, Q & Tamhankar, M 2016, Towards parallel implementation of associative inference for cogent confabulation. in 2016 IEEE High Performance Extreme Computing Conference, HPEC 2016., 7761623, Institute of Electrical and Electronics Engineers Inc., 2016 IEEE High Performance Extreme Computing Conference, HPEC 2016, Waltham, United States, 9/13/16. https://doi.org/10.1109/HPEC.2016.7761623
Li Z, Qiu Q, Tamhankar M. Towards parallel implementation of associative inference for cogent confabulation. In 2016 IEEE High Performance Extreme Computing Conference, HPEC 2016. Institute of Electrical and Electronics Engineers Inc. 2016. 7761623 https://doi.org/10.1109/HPEC.2016.7761623
Li, Zhe ; Qiu, Qinru ; Tamhankar, Mangesh. / Towards parallel implementation of associative inference for cogent confabulation. 2016 IEEE High Performance Extreme Computing Conference, HPEC 2016. Institute of Electrical and Electronics Engineers Inc., 2016.
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