Towards memristor based accelerator for sparse matrix vector multiplication

Jianwei Cui, Qinru Qiu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Citations (Scopus)

Abstract

In the last few years, memristor crossbar array is drawing increasing attention from the research community as a promising neuromorphic computing accelerator. In this work, we investigate the hardware acceleration of a sparse matrix vector (SpMV) multiplication engine based on memristor crossbar array. We demon strate that naive matrix coefficient mapping is infeasible and unpractical if the matrix has large dimensions. To combat this problem, we extend the traditional Cuthill-McKee algorithm used for matrix restructuring, and propose a generalized sparse matrix reordering (GSMR) technique, which leverages linear transformation to effectively break down any rectangular unsymmetrical matrices into minimum number of sub-blocks that fit into the reasonably sized crossbar array. Simulated results show that our proposed design achieves appealing p erformances in terms of speed and energy efficiency compared to both CPU and GPU platforms. In addition, a memristor crossbar array utilizing GSMR outperforms its counterpart with no-GSMR by 90% performance improvements and 44% energy reduction.

Original languageEnglish (US)
Title of host publicationISCAS 2016 - IEEE International Symposium on Circuits and Systems
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages121-124
Number of pages4
Volume2016-July
ISBN (Electronic)9781479953400
DOIs
StatePublished - Jul 29 2016
Event2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016 - Montreal, Canada
Duration: May 22 2016May 25 2016

Other

Other2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016
CountryCanada
CityMontreal
Period5/22/165/25/16

Fingerprint

Memristors
Particle accelerators
Drawing (graphics)
Linear transformations
Program processors
Energy efficiency
Engines
Hardware

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Cui, J., & Qiu, Q. (2016). Towards memristor based accelerator for sparse matrix vector multiplication. In ISCAS 2016 - IEEE International Symposium on Circuits and Systems (Vol. 2016-July, pp. 121-124). [7527185] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2016.7527185

Towards memristor based accelerator for sparse matrix vector multiplication. / Cui, Jianwei; Qiu, Qinru.

ISCAS 2016 - IEEE International Symposium on Circuits and Systems. Vol. 2016-July Institute of Electrical and Electronics Engineers Inc., 2016. p. 121-124 7527185.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Cui, J & Qiu, Q 2016, Towards memristor based accelerator for sparse matrix vector multiplication. in ISCAS 2016 - IEEE International Symposium on Circuits and Systems. vol. 2016-July, 7527185, Institute of Electrical and Electronics Engineers Inc., pp. 121-124, 2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016, Montreal, Canada, 5/22/16. https://doi.org/10.1109/ISCAS.2016.7527185
Cui J, Qiu Q. Towards memristor based accelerator for sparse matrix vector multiplication. In ISCAS 2016 - IEEE International Symposium on Circuits and Systems. Vol. 2016-July. Institute of Electrical and Electronics Engineers Inc. 2016. p. 121-124. 7527185 https://doi.org/10.1109/ISCAS.2016.7527185
Cui, Jianwei ; Qiu, Qinru. / Towards memristor based accelerator for sparse matrix vector multiplication. ISCAS 2016 - IEEE International Symposium on Circuits and Systems. Vol. 2016-July Institute of Electrical and Electronics Engineers Inc., 2016. pp. 121-124
@inproceedings{15e065a1aff24ac3af4388ee9d027a6e,
title = "Towards memristor based accelerator for sparse matrix vector multiplication",
abstract = "In the last few years, memristor crossbar array is drawing increasing attention from the research community as a promising neuromorphic computing accelerator. In this work, we investigate the hardware acceleration of a sparse matrix vector (SpMV) multiplication engine based on memristor crossbar array. We demon strate that naive matrix coefficient mapping is infeasible and unpractical if the matrix has large dimensions. To combat this problem, we extend the traditional Cuthill-McKee algorithm used for matrix restructuring, and propose a generalized sparse matrix reordering (GSMR) technique, which leverages linear transformation to effectively break down any rectangular unsymmetrical matrices into minimum number of sub-blocks that fit into the reasonably sized crossbar array. Simulated results show that our proposed design achieves appealing p erformances in terms of speed and energy efficiency compared to both CPU and GPU platforms. In addition, a memristor crossbar array utilizing GSMR outperforms its counterpart with no-GSMR by 90{\%} performance improvements and 44{\%} energy reduction.",
author = "Jianwei Cui and Qinru Qiu",
year = "2016",
month = "7",
day = "29",
doi = "10.1109/ISCAS.2016.7527185",
language = "English (US)",
volume = "2016-July",
pages = "121--124",
booktitle = "ISCAS 2016 - IEEE International Symposium on Circuits and Systems",
publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

TY - GEN

T1 - Towards memristor based accelerator for sparse matrix vector multiplication

AU - Cui, Jianwei

AU - Qiu, Qinru

PY - 2016/7/29

Y1 - 2016/7/29

N2 - In the last few years, memristor crossbar array is drawing increasing attention from the research community as a promising neuromorphic computing accelerator. In this work, we investigate the hardware acceleration of a sparse matrix vector (SpMV) multiplication engine based on memristor crossbar array. We demon strate that naive matrix coefficient mapping is infeasible and unpractical if the matrix has large dimensions. To combat this problem, we extend the traditional Cuthill-McKee algorithm used for matrix restructuring, and propose a generalized sparse matrix reordering (GSMR) technique, which leverages linear transformation to effectively break down any rectangular unsymmetrical matrices into minimum number of sub-blocks that fit into the reasonably sized crossbar array. Simulated results show that our proposed design achieves appealing p erformances in terms of speed and energy efficiency compared to both CPU and GPU platforms. In addition, a memristor crossbar array utilizing GSMR outperforms its counterpart with no-GSMR by 90% performance improvements and 44% energy reduction.

AB - In the last few years, memristor crossbar array is drawing increasing attention from the research community as a promising neuromorphic computing accelerator. In this work, we investigate the hardware acceleration of a sparse matrix vector (SpMV) multiplication engine based on memristor crossbar array. We demon strate that naive matrix coefficient mapping is infeasible and unpractical if the matrix has large dimensions. To combat this problem, we extend the traditional Cuthill-McKee algorithm used for matrix restructuring, and propose a generalized sparse matrix reordering (GSMR) technique, which leverages linear transformation to effectively break down any rectangular unsymmetrical matrices into minimum number of sub-blocks that fit into the reasonably sized crossbar array. Simulated results show that our proposed design achieves appealing p erformances in terms of speed and energy efficiency compared to both CPU and GPU platforms. In addition, a memristor crossbar array utilizing GSMR outperforms its counterpart with no-GSMR by 90% performance improvements and 44% energy reduction.

UR - http://www.scopus.com/inward/record.url?scp=84983377281&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84983377281&partnerID=8YFLogxK

U2 - 10.1109/ISCAS.2016.7527185

DO - 10.1109/ISCAS.2016.7527185

M3 - Conference contribution

AN - SCOPUS:84983377281

VL - 2016-July

SP - 121

EP - 124

BT - ISCAS 2016 - IEEE International Symposium on Circuits and Systems

PB - Institute of Electrical and Electronics Engineers Inc.

ER -