Thermal via planning aware force-directed floorplanning for D ICs

Yun Huang; Qiang Zhou; Yici Cai

doi:10.1109/ASICON.2009.5351314

Thermal via planning aware force-directed floorplanning for D ICs

Yun Huang, Qiang Zhou, Yici Cai

Research output: Chapter in Book/Entry/Poem › Conference contribution

Abstract

The three-dimensional (3D) integration circuit is a new technology with higher integration density and better performance than 2D ICs. To solve the critical thermal issue in 3D layout, we propose a force-directed jloorplanning algorithm. This algorithm naturally integrates with the planning ofthermal vias and reasonably allocates white space for inserting the thermal vias. It solves the problem of the thermal distribution disturbance by the white space reassignment. Compare with the after-jloorplanning thermal via planning algorithm, this algorithm decreases the number of thermal vias by 8.2% while increases the area by 3.5% on average.

Original language	English (US)
Title of host publication	ASICON 2009 - Proceedings, 2009 8th IEEE International Conference on ASIC
Pages	751-753
Number of pages	3
DOIs	https://doi.org/10.1109/ASICON.2009.5351314
State	Published - 2009
Externally published	Yes
Event	2009 8th IEEE International Conference on ASIC, ASICON 2009 - Changsha, China Duration: Oct 20 2009 → Oct 23 2009

Publication series

Name	ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC

Other

Other	2009 8th IEEE International Conference on ASIC, ASICON 2009
Country/Territory	China
City	Changsha
Period	10/20/09 → 10/23/09

Keywords

Floorplanning
Force-directed
Thermal via
Three-dimensional Integrated Circuits (3D ICs)

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ASICON.2009.5351314

Cite this

Huang, Y, Zhou, Q & Cai, Y 2009, Thermal via planning aware force-directed floorplanning for D ICs. in ASICON 2009 - Proceedings, 2009 8th IEEE International Conference on ASIC., 5351314, ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC, pp. 751-753, 2009 8th IEEE International Conference on ASIC, ASICON 2009, Changsha, China, 10/20/09. https://doi.org/10.1109/ASICON.2009.5351314

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title = "Thermal via planning aware force-directed floorplanning for D ICs",

abstract = "The three-dimensional (3D) integration circuit is a new technology with higher integration density and better performance than 2D ICs. To solve the critical thermal issue in 3D layout, we propose a force-directed jloorplanning algorithm. This algorithm naturally integrates with the planning ofthermal vias and reasonably allocates white space for inserting the thermal vias. It solves the problem of the thermal distribution disturbance by the white space reassignment. Compare with the after-jloorplanning thermal via planning algorithm, this algorithm decreases the number of thermal vias by 8.2% while increases the area by 3.5% on average.",

keywords = "Floorplanning, Force-directed, Thermal via, Three-dimensional Integrated Circuits (3D ICs)",

author = "Yun Huang and Qiang Zhou and Yici Cai",

year = "2009",

doi = "10.1109/ASICON.2009.5351314",

language = "English (US)",

isbn = "9781424438686",

series = "ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC",

pages = "751--753",

booktitle = "ASICON 2009 - Proceedings, 2009 8th IEEE International Conference on ASIC",

note = "2009 8th IEEE International Conference on ASIC, ASICON 2009 ; Conference date: 20-10-2009 Through 23-10-2009",

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AU - Huang, Yun

AU - Zhou, Qiang

AU - Cai, Yici

PY - 2009

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N2 - The three-dimensional (3D) integration circuit is a new technology with higher integration density and better performance than 2D ICs. To solve the critical thermal issue in 3D layout, we propose a force-directed jloorplanning algorithm. This algorithm naturally integrates with the planning ofthermal vias and reasonably allocates white space for inserting the thermal vias. It solves the problem of the thermal distribution disturbance by the white space reassignment. Compare with the after-jloorplanning thermal via planning algorithm, this algorithm decreases the number of thermal vias by 8.2% while increases the area by 3.5% on average.

AB - The three-dimensional (3D) integration circuit is a new technology with higher integration density and better performance than 2D ICs. To solve the critical thermal issue in 3D layout, we propose a force-directed jloorplanning algorithm. This algorithm naturally integrates with the planning ofthermal vias and reasonably allocates white space for inserting the thermal vias. It solves the problem of the thermal distribution disturbance by the white space reassignment. Compare with the after-jloorplanning thermal via planning algorithm, this algorithm decreases the number of thermal vias by 8.2% while increases the area by 3.5% on average.

KW - Floorplanning

KW - Force-directed

KW - Thermal via

KW - Three-dimensional Integrated Circuits (3D ICs)

UR - http://www.scopus.com/inward/record.url?scp=77949359277&partnerID=8YFLogxK

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DO - 10.1109/ASICON.2009.5351314

M3 - Conference contribution

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SN - 9781424438686

T3 - ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC

SP - 751

EP - 753

BT - ASICON 2009 - Proceedings, 2009 8th IEEE International Conference on ASIC

T2 - 2009 8th IEEE International Conference on ASIC, ASICON 2009

Y2 - 20 October 2009 through 23 October 2009

ER -

Thermal via planning aware force-directed floorplanning for D ICs

Abstract

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Keywords

ASJC Scopus subject areas

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