Thermal via planning aware force-directed floorplanning for D ICs

Yun Huang, Qiang Zhou, Yici Cai

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The three-dimensional (3D) integration circuit is a new technology with higher integration density and better performance than 2D ICs. To solve the critical thermal issue in 3D layout, we propose a force-directed jloorplanning algorithm. This algorithm naturally integrates with the planning ofthermal vias and reasonably allocates white space for inserting the thermal vias. It solves the problem of the thermal distribution disturbance by the white space reassignment. Compare with the after-jloorplanning thermal via planning algorithm, this algorithm decreases the number of thermal vias by 8.2% while increases the area by 3.5% on average.

Original languageEnglish (US)
Title of host publicationASICON 2009 - Proceedings, 2009 8th IEEE International Conference on ASIC
Pages751-753
Number of pages3
DOIs
StatePublished - Dec 1 2009
Event2009 8th IEEE International Conference on ASIC, ASICON 2009 - Changsha, China
Duration: Oct 20 2009Oct 23 2009

Publication series

NameASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC

Other

Other2009 8th IEEE International Conference on ASIC, ASICON 2009
CountryChina
CityChangsha
Period10/20/0910/23/09

Keywords

  • Floorplanning
  • Force-directed
  • Thermal via
  • Three-dimensional Integrated Circuits (3D ICs)

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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