The SALT—readout ASIC for silicon strip sensors of upstream tracker in the upgraded LHCb experiment

Carlos Abellan Beteta; Dimitra Andreou; Marina Artuso; Andy Beiter; Steven Blusk; Roma Bugiel; Szymon Bugiel; Antonio Carbone; Ina Carli; Bo Chen; Nadim Conti; Federico De Benedetti; Shuchong Ding; Scott Ely; Miroslaw Firlej; Tomasz Fiutowski; Paolo Gandini; Danielle Germann; Nathan Grieser; Marek Idzik; Xiaojie Jiang; Wojciech Krupa; Yiming Li; Zhuoming Li; Xixin Liang; Shuaiyi Liu; Yu Lu; Lauren Mackey; Jakub Moron; Ray Mountain; Marco Petruzzo; Hang Pham; Burkhard Schmidt; Shuqi Sheng; Elisabetta Spadaro Norella; Krzysztof Swientek; Tomasz Szumlak; Mark Tobin; Jianchun Wang; Michael Wilkinson; Hangyi Wu; Feihao Zhang; Quan Zou

doi:10.3390/s22010107

The SALT—readout ASIC for silicon strip sensors of upstream tracker in the upgraded LHCb experiment

Carlos Abellan Beteta, Dimitra Andreou, Marina Artuso, Andy Beiter, Steven Blusk, Roma Bugiel, Szymon Bugiel, Antonio Carbone, Ina Carli, Bo Chen, Nadim Conti, Federico De Benedetti, Shuchong Ding, Scott Ely, Miroslaw Firlej, Tomasz Fiutowski, Paolo Gandini, Danielle Germann, Nathan Grieser, Marek IdzikXiaojie Jiang, Wojciech Krupa, Yiming Li, Zhuoming Li, Xixin Liang, Shuaiyi Liu, Yu Lu, Lauren Mackey, Jakub Moron, Ray Mountain, Marco Petruzzo, Hang Pham, Burkhard Schmidt, Shuqi Sheng, Elisabetta Spadaro Norella, Krzysztof Swientek, Tomasz Szumlak, Mark Tobin, Jianchun Wang, Michael Wilkinson, Hangyi Wu, Feihao Zhang, Quan Zou

Department of Physics

Research output: Contribution to journal › Article › peer-review

1 Scopus citations

Abstract

SALT, a new dedicated readout Application Specific Integrated Circuit (ASIC) for the Upstream Tracker, a new silicon detector in the Large Hadron Collider beauty (LHCb) experiment, has been designed and developed. It is a 128-channel chip using an innovative architecture comprising a low-power analogue front-end with fast pulse shaping and a 40 MSps 6-bit Analog-to-Digital Converter (ADC) in each channel, followed by a Digital Signal Processing (DSP) block performing pedestal and Mean Common Mode (MCM) subtraction and zero suppression. The prototypes of SALT were fabricated and tested, confirming the full chip functionality and fulfilling the specifications. A signal-to-noise ratio of about 20 is achieved for a silicon sensor with a 12 pF input capacitance. In this paper, the SALT architecture and measurements of the chip performance are presented.

Original language	English (US)
Article number	107
Journal	Sensors
Volume	22
Issue number	1
DOIs	https://doi.org/10.3390/s22010107
State	Published - Jan 1 2022

Keywords

ADC
ASIC
DLL
DSP
Front-end
PLL
SEE

ASJC Scopus subject areas

Analytical Chemistry
Information Systems
Biochemistry
Atomic and Molecular Physics, and Optics
Instrumentation
Electrical and Electronic Engineering

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10.3390/s22010107

Cite this

Beteta, C. A., Andreou, D., Artuso, M., Beiter, A., Blusk, S., Bugiel, R., Bugiel, S., Carbone, A., Carli, I., Chen, B., Conti, N., De Benedetti, F., Ding, S., Ely, S., Firlej, M., Fiutowski, T., Gandini, P., Germann, D., Grieser, N., ... Zou, Q. (2022). The SALT—readout ASIC for silicon strip sensors of upstream tracker in the upgraded LHCb experiment. Sensors, 22(1), [107]. https://doi.org/10.3390/s22010107

Beteta, CA, Andreou, D, Artuso, M, Beiter, A, Blusk, S, Bugiel, R, Bugiel, S, Carbone, A, Carli, I, Chen, B, Conti, N, De Benedetti, F, Ding, S, Ely, S, Firlej, M, Fiutowski, T, Gandini, P, Germann, D, Grieser, N, Idzik, M, Jiang, X, Krupa, W, Li, Y, Li, Z, Liang, X, Liu, S, Lu, Y, Mackey, L, Moron, J, Mountain, R, Petruzzo, M, Pham, H, Schmidt, B, Sheng, S, Norella, ES, Swientek, K, Szumlak, T, Tobin, M, Wang, J, Wilkinson, M, Wu, H, Zhang, F & Zou, Q 2022, 'The SALT—readout ASIC for silicon strip sensors of upstream tracker in the upgraded LHCb experiment', Sensors, vol. 22, no. 1, 107. https://doi.org/10.3390/s22010107

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title = "The SALT—readout ASIC for silicon strip sensors of upstream tracker in the upgraded LHCb experiment",

abstract = "SALT, a new dedicated readout Application Specific Integrated Circuit (ASIC) for the Upstream Tracker, a new silicon detector in the Large Hadron Collider beauty (LHCb) experiment, has been designed and developed. It is a 128-channel chip using an innovative architecture comprising a low-power analogue front-end with fast pulse shaping and a 40 MSps 6-bit Analog-to-Digital Converter (ADC) in each channel, followed by a Digital Signal Processing (DSP) block performing pedestal and Mean Common Mode (MCM) subtraction and zero suppression. The prototypes of SALT were fabricated and tested, confirming the full chip functionality and fulfilling the specifications. A signal-to-noise ratio of about 20 is achieved for a silicon sensor with a 12 pF input capacitance. In this paper, the SALT architecture and measurements of the chip performance are presented.",

keywords = "ADC, ASIC, DLL, DSP, Front-end, PLL, SEE",

author = "Beteta, {Carlos Abellan} and Dimitra Andreou and Marina Artuso and Andy Beiter and Steven Blusk and Roma Bugiel and Szymon Bugiel and Antonio Carbone and Ina Carli and Bo Chen and Nadim Conti and {De Benedetti}, Federico and Shuchong Ding and Scott Ely and Miroslaw Firlej and Tomasz Fiutowski and Paolo Gandini and Danielle Germann and Nathan Grieser and Marek Idzik and Xiaojie Jiang and Wojciech Krupa and Yiming Li and Zhuoming Li and Xixin Liang and Shuaiyi Liu and Yu Lu and Lauren Mackey and Jakub Moron and Ray Mountain and Marco Petruzzo and Hang Pham and Burkhard Schmidt and Shuqi Sheng and Norella, {Elisabetta Spadaro} and Krzysztof Swientek and Tomasz Szumlak and Mark Tobin and Jianchun Wang and Michael Wilkinson and Hangyi Wu and Feihao Zhang and Quan Zou",

note = "Funding Information: Funding: This research was funded by Ministry of Science and Higher Education of Poland grant number MEiN DIR/WK/2017/2020/04-1. N. Conti, F. De Benedetti, A. Merli, M. Petruzzo, E. Spadaro Norella were supported from the ERC Consolidator Grant SELDOM G.A. 771642. The APC was funded by European Organization for Nuclear Research (CERN). Publisher Copyright: {\textcopyright} 2021 by the authors. Licensee MDPI, Basel, Switzerland.",

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AU - Beteta, Carlos Abellan

AU - Andreou, Dimitra

AU - Artuso, Marina

AU - Beiter, Andy

AU - Blusk, Steven

AU - Bugiel, Roma

AU - Bugiel, Szymon

AU - Carbone, Antonio

AU - Carli, Ina

AU - Chen, Bo

AU - Conti, Nadim

AU - De Benedetti, Federico

AU - Ding, Shuchong

AU - Ely, Scott

AU - Firlej, Miroslaw

AU - Fiutowski, Tomasz

AU - Gandini, Paolo

AU - Germann, Danielle

AU - Grieser, Nathan

AU - Idzik, Marek

AU - Jiang, Xiaojie

AU - Krupa, Wojciech

AU - Li, Yiming

AU - Li, Zhuoming

AU - Liang, Xixin

AU - Liu, Shuaiyi

AU - Lu, Yu

AU - Mackey, Lauren

AU - Moron, Jakub

AU - Mountain, Ray

AU - Petruzzo, Marco

AU - Pham, Hang

AU - Schmidt, Burkhard

AU - Sheng, Shuqi

AU - Norella, Elisabetta Spadaro

AU - Swientek, Krzysztof

AU - Szumlak, Tomasz

AU - Tobin, Mark

AU - Wang, Jianchun

AU - Wilkinson, Michael

AU - Wu, Hangyi

AU - Zhang, Feihao

AU - Zou, Quan

N1 - Funding Information: Funding: This research was funded by Ministry of Science and Higher Education of Poland grant number MEiN DIR/WK/2017/2020/04-1. N. Conti, F. De Benedetti, A. Merli, M. Petruzzo, E. Spadaro Norella were supported from the ERC Consolidator Grant SELDOM G.A. 771642. The APC was funded by European Organization for Nuclear Research (CERN). Publisher Copyright: © 2021 by the authors. Licensee MDPI, Basel, Switzerland.

PY - 2022/1/1

Y1 - 2022/1/1

N2 - SALT, a new dedicated readout Application Specific Integrated Circuit (ASIC) for the Upstream Tracker, a new silicon detector in the Large Hadron Collider beauty (LHCb) experiment, has been designed and developed. It is a 128-channel chip using an innovative architecture comprising a low-power analogue front-end with fast pulse shaping and a 40 MSps 6-bit Analog-to-Digital Converter (ADC) in each channel, followed by a Digital Signal Processing (DSP) block performing pedestal and Mean Common Mode (MCM) subtraction and zero suppression. The prototypes of SALT were fabricated and tested, confirming the full chip functionality and fulfilling the specifications. A signal-to-noise ratio of about 20 is achieved for a silicon sensor with a 12 pF input capacitance. In this paper, the SALT architecture and measurements of the chip performance are presented.

AB - SALT, a new dedicated readout Application Specific Integrated Circuit (ASIC) for the Upstream Tracker, a new silicon detector in the Large Hadron Collider beauty (LHCb) experiment, has been designed and developed. It is a 128-channel chip using an innovative architecture comprising a low-power analogue front-end with fast pulse shaping and a 40 MSps 6-bit Analog-to-Digital Converter (ADC) in each channel, followed by a Digital Signal Processing (DSP) block performing pedestal and Mean Common Mode (MCM) subtraction and zero suppression. The prototypes of SALT were fabricated and tested, confirming the full chip functionality and fulfilling the specifications. A signal-to-noise ratio of about 20 is achieved for a silicon sensor with a 12 pF input capacitance. In this paper, the SALT architecture and measurements of the chip performance are presented.

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KW - Front-end

KW - PLL

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ER -

The SALT—readout ASIC for silicon strip sensors of upstream tracker in the upgraded LHCb experiment

Abstract

Keywords

ASJC Scopus subject areas

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