TY - JOUR
T1 - Technique for 1-dimensional VLSI layout generation
AU - Singh, U.
AU - Chen, C. Y.R.
PY - 1992
Y1 - 1992
N2 - The layout and synthesis system RESCUE presented by Shaw et al. is briefly reviewed. It is a system for implementing random logic using an array layout style. RTL equations are realized by a horizontal row of cells which may contain both static and dynamic circuits. Signals are carried by polysilicon lines in horizontal rows. Algorithmic improvements are suggested in three areas. First, the mincut algorithm is proposed for the cell-assignment problem. Secondly, a new algorithm is presented which determines a placement for the polysilicon lines in a way that allows narrower cells to be designed. Another algorithm based on a technique developed by the authors is proposed for designing cells so as to optimize their areas. The complexity of the final set of algorithms is O(E log E) where E is the number of RTL equations. Improvements range from 5.5% to 50%.
AB - The layout and synthesis system RESCUE presented by Shaw et al. is briefly reviewed. It is a system for implementing random logic using an array layout style. RTL equations are realized by a horizontal row of cells which may contain both static and dynamic circuits. Signals are carried by polysilicon lines in horizontal rows. Algorithmic improvements are suggested in three areas. First, the mincut algorithm is proposed for the cell-assignment problem. Secondly, a new algorithm is presented which determines a placement for the polysilicon lines in a way that allows narrower cells to be designed. Another algorithm based on a technique developed by the authors is proposed for designing cells so as to optimize their areas. The complexity of the final set of algorithms is O(E log E) where E is the number of RTL equations. Improvements range from 5.5% to 50%.
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U2 - 10.1049/ip-g-2.1992.0097
DO - 10.1049/ip-g-2.1992.0097
M3 - Article
AN - SCOPUS:0027002319
SN - 0956-3768
VL - 139
SP - 635
EP - 645
JO - IEE Proceedings, Part G: Circuits, Devices and Systems
JF - IEE Proceedings, Part G: Circuits, Devices and Systems
IS - 6
ER -