Abstract
The emerging field of neuromorphic computing is offering a possible pathway for approaching the brain's computing performance and energy efficiency for cognitive applications such as pattern recognition, speech understanding, natural language processing etc. In spiking neural networks (SNNs), information is encoded as sparsely distributed spike trains, enabling learning through the spike-timing dependent plasticity (STDP) mechanism. SNNs can potentially achieve ultra-low power consumption and distributed learning due to the inherent asynchronous and sparse inter-neuron communications. Several inroads have been made in SNN implementations, however, there is still a lack of computational models that lead to hardware implementation of large scale SNN with STDP capabilities. In this work, we present a set of neuron models and neuron circuit motifs that form SNNs capable of in-hardware fully-distributed STDP learning and spiking based probabilistic inference. Functions such as efficient Bayesian inference and unsupervised Hebbian learning are demonstrated on the proposed SNN system design. A highly scalable and flexible digital hardware implementation of the neuron model is also presented. Experimental results on two different applications: unsupervised feature extraction and inference based sentence construction, have demonstrated the proposed design's effectiveness in learning and inference.
| Original language | English (US) |
|---|---|
| Title of host publication | Proceedings - IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2016 |
| Publisher | IEEE Computer Society |
| Pages | 272-277 |
| Number of pages | 6 |
| Volume | 2016-September |
| ISBN (Electronic) | 9781467390385 |
| DOIs | |
| State | Published - Sep 2 2016 |
| Event | 15th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2016 - Pittsburgh, United States Duration: Jul 11 2016 → Jul 13 2016 |
Other
| Other | 15th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2016 |
|---|---|
| Country | United States |
| City | Pittsburgh |
| Period | 7/11/16 → 7/13/16 |
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Keywords
- Bayesian inference
- Bayesian neuron
- digital neuron
- Spiking neural network
- STDP Learning
- unsupervised feature learning
- winner-take-all
ASJC Scopus subject areas
- Hardware and Architecture
- Control and Systems Engineering
- Electrical and Electronic Engineering
Cite this
System design for in-hardware STDP learning and spiking based probablistic inference. / Ahmed, Khadeer; Shrestha, Amar; Wang, Yanzhi; Qiu, Qinru.
Proceedings - IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2016. Vol. 2016-September IEEE Computer Society, 2016. p. 272-277 7560209.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - System design for in-hardware STDP learning and spiking based probablistic inference
AU - Ahmed, Khadeer
AU - Shrestha, Amar
AU - Wang, Yanzhi
AU - Qiu, Qinru
PY - 2016/9/2
Y1 - 2016/9/2
N2 - The emerging field of neuromorphic computing is offering a possible pathway for approaching the brain's computing performance and energy efficiency for cognitive applications such as pattern recognition, speech understanding, natural language processing etc. In spiking neural networks (SNNs), information is encoded as sparsely distributed spike trains, enabling learning through the spike-timing dependent plasticity (STDP) mechanism. SNNs can potentially achieve ultra-low power consumption and distributed learning due to the inherent asynchronous and sparse inter-neuron communications. Several inroads have been made in SNN implementations, however, there is still a lack of computational models that lead to hardware implementation of large scale SNN with STDP capabilities. In this work, we present a set of neuron models and neuron circuit motifs that form SNNs capable of in-hardware fully-distributed STDP learning and spiking based probabilistic inference. Functions such as efficient Bayesian inference and unsupervised Hebbian learning are demonstrated on the proposed SNN system design. A highly scalable and flexible digital hardware implementation of the neuron model is also presented. Experimental results on two different applications: unsupervised feature extraction and inference based sentence construction, have demonstrated the proposed design's effectiveness in learning and inference.
AB - The emerging field of neuromorphic computing is offering a possible pathway for approaching the brain's computing performance and energy efficiency for cognitive applications such as pattern recognition, speech understanding, natural language processing etc. In spiking neural networks (SNNs), information is encoded as sparsely distributed spike trains, enabling learning through the spike-timing dependent plasticity (STDP) mechanism. SNNs can potentially achieve ultra-low power consumption and distributed learning due to the inherent asynchronous and sparse inter-neuron communications. Several inroads have been made in SNN implementations, however, there is still a lack of computational models that lead to hardware implementation of large scale SNN with STDP capabilities. In this work, we present a set of neuron models and neuron circuit motifs that form SNNs capable of in-hardware fully-distributed STDP learning and spiking based probabilistic inference. Functions such as efficient Bayesian inference and unsupervised Hebbian learning are demonstrated on the proposed SNN system design. A highly scalable and flexible digital hardware implementation of the neuron model is also presented. Experimental results on two different applications: unsupervised feature extraction and inference based sentence construction, have demonstrated the proposed design's effectiveness in learning and inference.
KW - Bayesian inference
KW - Bayesian neuron
KW - digital neuron
KW - Spiking neural network
KW - STDP Learning
KW - unsupervised feature learning
KW - winner-take-all
UR - http://www.scopus.com/inward/record.url?scp=84988953258&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84988953258&partnerID=8YFLogxK
U2 - 10.1109/ISVLSI.2016.91
DO - 10.1109/ISVLSI.2016.91
M3 - Conference contribution
AN - SCOPUS:84988953258
VL - 2016-September
SP - 272
EP - 277
BT - Proceedings - IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2016
PB - IEEE Computer Society
ER -