TY - GEN
T1 - Synthesis of application-specific multiprocessor systems
AU - Dhodhi, Muhammad Khan
AU - Ahmad, Imtiaz
AU - Chen, C. Y.Roger
PY - 1994
Y1 - 1994
N2 - The current VLSI/ULSI technology enables the implementation of a complicated system in a single chip at a low cost. Thus it has become cost effective to design special-purpose multiprocessor architectures for computational-intensive applications in signal processing, control of power systems and robotics. In this paper, we introduce a novel design methodology based on the problem-space genetic algorithms for the synthesis of application-specific multiprocessor systems to meet the various cost and performance constraints, not merely the mapping of tasks onto a given system. The design methodology for the synthesis of a custom heterogeneous multiprocessor system selects the number and type of processor, finds an interconnection pattern between processors, maps the subtasks onto the system and provides a static schedule for the subtasks execution for a given application specified in terms of a task flow graph.
AB - The current VLSI/ULSI technology enables the implementation of a complicated system in a single chip at a low cost. Thus it has become cost effective to design special-purpose multiprocessor architectures for computational-intensive applications in signal processing, control of power systems and robotics. In this paper, we introduce a novel design methodology based on the problem-space genetic algorithms for the synthesis of application-specific multiprocessor systems to meet the various cost and performance constraints, not merely the mapping of tasks onto a given system. The design methodology for the synthesis of a custom heterogeneous multiprocessor system selects the number and type of processor, finds an interconnection pattern between processors, maps the subtasks onto the system and provides a static schedule for the subtasks execution for a given application specified in terms of a task flow graph.
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M3 - Conference contribution
AN - SCOPUS:0028026365
SN - 0818654112
T3 - Proceedings of the European Design and Test Conference
SP - 671
BT - Proceedings of the European Design and Test Conference
A2 - Anon, null
PB - IEEE Computer Society
T2 - Proceedings of the European Design and Test Conference
Y2 - 28 February 1994 through 3 March 1994
ER -