@inproceedings{4c90e22ec69a4ac9ba3f99e04b96f781,
title = "Standard cell library based layout characterization and power analysis for 10nm gate-all-around (GAA) transistors",
abstract = "Gate-all-around (GAA) nanowire transistor is promising for continuing scaling down the feature size of transistors beyond sub-10nm because it provides the gate with better controllability over the channel by wrapping around. In this paper, the device model for 10nm gate length conventional GAA (C-GAA) and junctionless GAA (JL-GAA) are extracted based on the TCAD simulation. The layout design of GAA transistors are characterized for different sizing methods. Liberty-formatted standard cell libraries are constructed by appropriately sizing pull-up and pull-down networks of each logic cell. Based on the library, power densities of 10nm technology node C-GAA and JL-GAA are analyzed under benchmark circuits in comparing with 7nm FinFET technology. Experimental results show that the vertical C-GAA transistor can achieve 28% area reduction and the horizontal C-GAA transistor can reduce 29% power consumption comparing with other C-GAA geometries. The power density of JL-GAA circuits can reach above the limit of air cooling and thermal management techniques are needed for JL-GAA circuits.",
author = "Luhao Wang and Tiansong Cui and Shahin Nazarian and Yanzhi Wang and Massoud Pedram",
note = "Publisher Copyright: {\textcopyright} 2016 IEEE.; 29th IEEE International System on Chip Conference, SOCC 2016 ; Conference date: 06-09-2016 Through 09-09-2016",
year = "2016",
month = jul,
day = "2",
doi = "10.1109/SOCC.2016.7905480",
language = "English (US)",
series = "International System on Chip Conference",
publisher = "IEEE Computer Society",
pages = "253--258",
editor = "Karan Bhatia and Massimo Alioto and Danella Zhao and Andrew Marshall and Ramalingam Sridhar",
booktitle = "Proceedings - 29th IEEE International System on Chip Conference, SOCC 2016",
address = "United States",
}