Standard cell library based layout characterization and power analysis for 10nm gate-all-around (GAA) transistors

Luhao Wang, Tiansong Cui, Shahin Nazarian, Yanzhi Wang, Massoud Pedram

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

Gate-all-around (GAA) nanowire transistor is promising for continuing scaling down the feature size of transistors beyond sub-10nm because it provides the gate with better controllability over the channel by wrapping around. In this paper, the device model for 10nm gate length conventional GAA (C-GAA) and junctionless GAA (JL-GAA) are extracted based on the TCAD simulation. The layout design of GAA transistors are characterized for different sizing methods. Liberty-formatted standard cell libraries are constructed by appropriately sizing pull-up and pull-down networks of each logic cell. Based on the library, power densities of 10nm technology node C-GAA and JL-GAA are analyzed under benchmark circuits in comparing with 7nm FinFET technology. Experimental results show that the vertical C-GAA transistor can achieve 28% area reduction and the horizontal C-GAA transistor can reduce 29% power consumption comparing with other C-GAA geometries. The power density of JL-GAA circuits can reach above the limit of air cooling and thermal management techniques are needed for JL-GAA circuits.

Original languageEnglish (US)
Title of host publicationProceedings - 29th IEEE International System on Chip Conference, SOCC 2016
PublisherIEEE Computer Society
Pages253-258
Number of pages6
ISBN (Electronic)9781509013661
DOIs
StatePublished - Apr 19 2017
Event29th IEEE International System on Chip Conference, SOCC 2016 - Seattle, United States
Duration: Sep 6 2016Sep 9 2016

Other

Other29th IEEE International System on Chip Conference, SOCC 2016
CountryUnited States
CitySeattle
Period9/6/169/9/16

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ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering
  • Electrical and Electronic Engineering

Cite this

Wang, L., Cui, T., Nazarian, S., Wang, Y., & Pedram, M. (2017). Standard cell library based layout characterization and power analysis for 10nm gate-all-around (GAA) transistors. In Proceedings - 29th IEEE International System on Chip Conference, SOCC 2016 (pp. 253-258). [7905480] IEEE Computer Society. https://doi.org/10.1109/SOCC.2016.7905480