Gate-all-around (GAA) nanowire transistor is promising for continuing scaling down the feature size of transistors beyond sub-10nm because it provides the gate with better controllability over the channel by wrapping around. In this paper, the device model for 10nm gate length conventional GAA (C-GAA) and junctionless GAA (JL-GAA) are extracted based on the TCAD simulation. The layout design of GAA transistors are characterized for different sizing methods. Liberty-formatted standard cell libraries are constructed by appropriately sizing pull-up and pull-down networks of each logic cell. Based on the library, power densities of 10nm technology node C-GAA and JL-GAA are analyzed under benchmark circuits in comparing with 7nm FinFET technology. Experimental results show that the vertical C-GAA transistor can achieve 28% area reduction and the horizontal C-GAA transistor can reduce 29% power consumption comparing with other C-GAA geometries. The power density of JL-GAA circuits can reach above the limit of air cooling and thermal management techniques are needed for JL-GAA circuits.