Stack sizing analysis and optimization for FinFET logic cells and circuits operating in the sub/near-threshold regime

Xue Lin, Yanzhi Wang, Massoud Pedram

Research output: Chapter in Book/Report/Conference proceedingConference contribution

15 Scopus citations

Abstract

Sub/near-threshold computing has been proposed for ultra-low power applications. FinFET devices are considered as an alternative for bulk CMOS devices due to the superior characteristics, which make FinFET an excellent candidate for ultra-low power designs. In this paper, we first present an improved analytical FinFET model covering both sub- and near-threshold regimes. This model accurately captures the drain current as a function of both the gate and drain voltages. Based on the accurate FinFET model, we provide a detailed analysis on stack sizing of FinFET logic cells, and derive the optimal stack depth in FinFET circuits. We also provide a delay optimization framework for the FinFET circuits in the sub/near-threshold region, based on the stack sizing analysis. To the best of our knowledge, this is the first work that provides in-depth analysis of the stack sizing of FinFET logic cells in the sub/near-threshold region based on the accurate FinFET modeling. Experimental results on the 32nm Predictive Technology Model for FinFET devices demonstrate the effectiveness of the proposed optimization framework.

Original languageEnglish (US)
Title of host publicationProceedings of the 15th International Symposium on Quality Electronic Design, ISQED 2014
PublisherIEEE Computer Society
Pages341-348
Number of pages8
ISBN (Print)9781479939466
DOIs
StatePublished - Jan 1 2014
Event15th International Symposium on Quality Electronic Design, ISQED 2014 - Santa Clara, CA, United States
Duration: Mar 3 2014Mar 5 2014

Publication series

NameProceedings - International Symposium on Quality Electronic Design, ISQED
ISSN (Print)1948-3287
ISSN (Electronic)1948-3295

Other

Other15th International Symposium on Quality Electronic Design, ISQED 2014
CountryUnited States
CitySanta Clara, CA
Period3/3/143/5/14

Keywords

  • FinFET device
  • Stack sizing
  • Sub/near-threshold

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

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    Lin, X., Wang, Y., & Pedram, M. (2014). Stack sizing analysis and optimization for FinFET logic cells and circuits operating in the sub/near-threshold regime. In Proceedings of the 15th International Symposium on Quality Electronic Design, ISQED 2014 (pp. 341-348). [6783346] (Proceedings - International Symposium on Quality Electronic Design, ISQED). IEEE Computer Society. https://doi.org/10.1109/ISQED.2014.6783346