Sensitivity based placer for standard cells

Bill Halpin, Chien Yi Roger Chen, Naresh Sehgal

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Scopus citations

Abstract

We present a new timing driven method for global placement. Our method is based on the observation that similar net length reductions in the different nets that make up a path may not impact the path delay in the same way. For each net in the design, we compute the net sensitivity, or the path delay reduction as a result of net length improvements. We use very accurate delay models that include the impact of waveform slope and driver loading effects. Our new timing driven algorithm uses the sensitivity information to focus on nets that have the greatest impact on improving the worst circuit paths. Our method significantly improves the worst path delay over existing published work on industry circuits.

Original languageEnglish (US)
Title of host publicationProceedings of the IEEE Great Lakes Symposium on VLSI
PublisherIEEE Computer Society
Pages193-196
Number of pages4
StatePublished - 2000
Externally publishedYes
EventGLSVLSI 2000: 10th Great Lakes Symposium on VLSI - Chicago, IL, USA
Duration: Mar 2 2000Mar 4 2000

Other

OtherGLSVLSI 2000: 10th Great Lakes Symposium on VLSI
CityChicago, IL, USA
Period3/2/003/4/00

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • Cite this

    Halpin, B., Chen, C. Y. R., & Sehgal, N. (2000). Sensitivity based placer for standard cells. In Proceedings of the IEEE Great Lakes Symposium on VLSI (pp. 193-196). IEEE Computer Society.