Scalable NoC-based Neuromorphic Hardware Learning and Inference

Haowen Fang; Amar Shrestha; Ma De Ma; Qinru Qiu

doi:10.1109/IJCNN.2018.8489619

Scalable NoC-based Neuromorphic Hardware Learning and Inference

Haowen Fang, Amar Shrestha, Ma De Ma, Qinru Qiu

Department of Electrical Engineering & Computer Science

Research output: Chapter in Book/Entry/Poem › Conference contribution

24 Scopus citations

Abstract

Bio-inspired neuromorphic hardware is a research direction to approach brain's computational power and energy efficiency. Spiking neural networks (SNN) encode information as sparsely distributed spike trains and employ spike-timingdependent plasticity (STDP) mechanism for learning. Existing hardware implementations of SNN are limited in scale or do not have in-hardware learning capability. In this work, we propose a low-cost scalable Network-on-Chip (NoC) based SNN hardware architecture with fully distributed in-hardware STDP learning capability. All hardware neurons work in parallel and communicate through the NoC. This enables chip-level interconnection, scalability and reconfigurability necessary for deploying different applications. The hardware is applied to learn MNIST digits as an evaluation of its learning capability. We explore the design space to study the trade-offs between speed, area and energy. How to use this procedure to find optimal architecture configuration is also discussed.

Original language	English (US)
Title of host publication	2018 International Joint Conference on Neural Networks, IJCNN 2018 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781509060146
DOIs	https://doi.org/10.1109/IJCNN.2018.8489619
State	Published - Oct 10 2018
Event	2018 International Joint Conference on Neural Networks, IJCNN 2018 - Rio de Janeiro, Brazil Duration: Jul 8 2018 → Jul 13 2018

Publication series

Name	Proceedings of the International Joint Conference on Neural Networks
Volume	2018-July

Other

Other	2018 International Joint Conference on Neural Networks, IJCNN 2018
Country/Territory	Brazil
City	Rio de Janeiro
Period	7/8/18 → 7/13/18

Keywords

Network on chip
STDP learning
Spiking neural network
Unsupervised learning

ASJC Scopus subject areas

Software
Artificial Intelligence

Access to Document

10.1109/IJCNN.2018.8489619

Cite this

Fang, H., Shrestha, A., De Ma, M., & Qiu, Q. (2018). Scalable NoC-based Neuromorphic Hardware Learning and Inference. In 2018 International Joint Conference on Neural Networks, IJCNN 2018 - Proceedings Article 8489619 (Proceedings of the International Joint Conference on Neural Networks; Vol. 2018-July). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IJCNN.2018.8489619

Scalable NoC-based Neuromorphic Hardware Learning and Inference. / Fang, Haowen; Shrestha, Amar; De Ma, Ma et al.
2018 International Joint Conference on Neural Networks, IJCNN 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2018. 8489619 (Proceedings of the International Joint Conference on Neural Networks; Vol. 2018-July).

Research output: Chapter in Book/Entry/Poem › Conference contribution

Fang, H, Shrestha, A, De Ma, M & Qiu, Q 2018, Scalable NoC-based Neuromorphic Hardware Learning and Inference. in 2018 International Joint Conference on Neural Networks, IJCNN 2018 - Proceedings., 8489619, Proceedings of the International Joint Conference on Neural Networks, vol. 2018-July, Institute of Electrical and Electronics Engineers Inc., 2018 International Joint Conference on Neural Networks, IJCNN 2018, Rio de Janeiro, Brazil, 7/8/18. https://doi.org/10.1109/IJCNN.2018.8489619

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Scalable NoC-based Neuromorphic Hardware Learning and Inference

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Keywords

ASJC Scopus subject areas

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