Abstract
Architects of multicore chips for avionics must define and bound intercore interference, which requires assuming a constant worst-case execution time for tasks executing on the chip. With the Single Core Equivalent technology package, engineers can treat each core as if it were a single-core chip.
Original language | English (US) |
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Pages | 69-77 |
Number of pages | 9 |
Volume | 49 |
No | 9 |
Specialist publication | Computer |
DOIs | |
State | Published - Sep 2016 |
Externally published | Yes |
Keywords
- avionics computing
- memory-access conflicts
- multicore architecture
- multicore chips
- multicore processing
- real-time systems
- single-core equivalence
ASJC Scopus subject areas
- General Computer Science