TY - GEN
T1 - Profiling and comparison of internal electrical environments of p and n-channel SOI MOSFETs
AU - Mody, J.
AU - Venkatachalam, A.
AU - Rodrigues, O.
AU - Jambulingam, S.
AU - Ghosh, P.
N1 - Publisher Copyright:
©2003 IEEE.
PY - 2003
Y1 - 2003
N2 - Internal electrical environment of p-channel SOI MOSFET is simulated and compared with the properties of n-channel SOI MOSFET. Electrical characteristics are modified due to the charge redistribution resulting from the applied bias voltage. Effects of channel shrinkage, for both n- and p-channel have been documented.
AB - Internal electrical environment of p-channel SOI MOSFET is simulated and compared with the properties of n-channel SOI MOSFET. Electrical characteristics are modified due to the charge redistribution resulting from the applied bias voltage. Effects of channel shrinkage, for both n- and p-channel have been documented.
UR - http://www.scopus.com/inward/record.url?scp=84946430054&partnerID=8YFLogxK
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U2 - 10.1109/EDSSC.2003.1283527
DO - 10.1109/EDSSC.2003.1283527
M3 - Conference contribution
AN - SCOPUS:84946430054
T3 - 2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003
SP - 259
EP - 262
BT - 2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003
Y2 - 16 December 2003 through 18 December 2003
ER -