Profiling and comparison of internal electrical environments of p and n-channel SOI MOSFETs

J. Mody; A. Venkatachalam; O. Rodrigues; S. Jambulingam; P. Ghosh

doi:10.1109/EDSSC.2003.1283527

Profiling and comparison of internal electrical environments of p and n-channel SOI MOSFETs

J. Mody, A. Venkatachalam, O. Rodrigues, S. Jambulingam, P. Ghosh

Department of Electrical Engineering & Computer Science

Research output: Chapter in Book/Entry/Poem › Conference contribution

1 Scopus citations

Abstract

Internal electrical environment of p-channel SOI MOSFET is simulated and compared with the properties of n-channel SOI MOSFET. Electrical characteristics are modified due to the charge redistribution resulting from the applied bias voltage. Effects of channel shrinkage, for both n- and p-channel have been documented.

Original language	English (US)
Title of host publication	2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	259-262
Number of pages	4
ISBN (Print)	0780377494, 9780780377493
DOIs	https://doi.org/10.1109/EDSSC.2003.1283527
State	Published - 2003
Event	IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003 - Tsimshatsui, Kowloon, Hong Kong Duration: Dec 16 2003 → Dec 18 2003

Other

Other	IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003
Country/Territory	Hong Kong
City	Tsimshatsui, Kowloon
Period	12/16/03 → 12/18/03

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/EDSSC.2003.1283527

Cite this

Mody, J., Venkatachalam, A., Rodrigues, O., Jambulingam, S., & Ghosh, P. (2003). Profiling and comparison of internal electrical environments of p and n-channel SOI MOSFETs. In 2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003 (pp. 259-262). Article 1283527 Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/EDSSC.2003.1283527

Profiling and comparison of internal electrical environments of p and n-channel SOI MOSFETs. / Mody, J.; Venkatachalam, A.; Rodrigues, O. et al.
2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003. Institute of Electrical and Electronics Engineers Inc., 2003. p. 259-262 1283527.

Research output: Chapter in Book/Entry/Poem › Conference contribution

Mody, J, Venkatachalam, A, Rodrigues, O, Jambulingam, S & Ghosh, P 2003, Profiling and comparison of internal electrical environments of p and n-channel SOI MOSFETs. in 2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003., 1283527, Institute of Electrical and Electronics Engineers Inc., pp. 259-262, IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003, Tsimshatsui, Kowloon, Hong Kong, 12/16/03. https://doi.org/10.1109/EDSSC.2003.1283527

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abstract = "Internal electrical environment of p-channel SOI MOSFET is simulated and compared with the properties of n-channel SOI MOSFET. Electrical characteristics are modified due to the charge redistribution resulting from the applied bias voltage. Effects of channel shrinkage, for both n- and p-channel have been documented.",

author = "J. Mody and A. Venkatachalam and O. Rodrigues and S. Jambulingam and P. Ghosh",

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ER -

Profiling and comparison of internal electrical environments of p and n-channel SOI MOSFETs

Abstract

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ASJC Scopus subject areas

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