TY - GEN
T1 - Power optimization for conditional task graphs in DVS enabled multiprocessor systems
AU - Malani, Parth
AU - Mukre, Prakash
AU - Qiu, Qinru
PY - 2007
Y1 - 2007
N2 - In this paper, we focus on power optimization of real-time applications with conditional execution running on a dynamic voltage scaling (DVS) enabled multiprocessor system. The targeted system consists of heterogeneous processing elements with non-negligible inter-processor communication delay and energy. Given a conditional task graph (CTG), we have developed novel online and offline algorithms that perform simultaneous task mapping and ordering followed by task stretching. Both algorithms minimize the mathematical expectation of energy dissipation of non-deterministic applications by considering the probabilistic distribution of branch selection. Compared with existing CTG scheduling algorithms, our online and offline scheduling algorithms reduce energy by 28% and 39% in average, respectively.
AB - In this paper, we focus on power optimization of real-time applications with conditional execution running on a dynamic voltage scaling (DVS) enabled multiprocessor system. The targeted system consists of heterogeneous processing elements with non-negligible inter-processor communication delay and energy. Given a conditional task graph (CTG), we have developed novel online and offline algorithms that perform simultaneous task mapping and ordering followed by task stretching. Both algorithms minimize the mathematical expectation of energy dissipation of non-deterministic applications by considering the probabilistic distribution of branch selection. Compared with existing CTG scheduling algorithms, our online and offline scheduling algorithms reduce energy by 28% and 39% in average, respectively.
UR - http://www.scopus.com/inward/record.url?scp=50149116607&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=50149116607&partnerID=8YFLogxK
U2 - 10.1109/VLSISOC.2007.4402503
DO - 10.1109/VLSISOC.2007.4402503
M3 - Conference contribution
AN - SCOPUS:50149116607
SN - 9781424417100
T3 - 2007 IFIP International Conference on Very Large Scale Integration, VLSI-SoC
SP - 230
EP - 235
BT - 2007 IFIP International Conference on Very Large Scale Integration, VLSI-SoC
T2 - 2007 IFIP International Conference on Very Large Scale Integration, VLSI-SoC
Y2 - 15 October 2007 through 17 October 2007
ER -