Power optimization for conditional task graphs in DVS enabled multiprocessor systems

Parth Malani, Prakash Mukre, Qinru Qiu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

In this paper, we focus on power optimization of real-time applications with conditional execution running on a dynamic voltage scaling (DVS) enabled multiprocessor system. The targeted system consists of heterogeneous processing elements with non-negligible inter-processor communication delay and energy. Given a conditional task graph (CTG), we have developed novel online and offline algorithms that perform simultaneous task mapping and ordering followed by task stretching. Both algorithms minimize the mathematical expectation of energy dissipation of non-deterministic applications by considering the probabilistic distribution of branch selection. Compared with existing CTG scheduling algorithms, our online and offline scheduling algorithms reduce energy by 28% and 39% in average, respectively.

Original languageEnglish (US)
Title of host publication2007 IFIP International Conference on Very Large Scale Integration, VLSI-SoC
Pages230-235
Number of pages6
DOIs
StatePublished - Dec 1 2007
Externally publishedYes
Event2007 IFIP International Conference on Very Large Scale Integration, VLSI-SoC - Atlanta, GA, United States
Duration: Oct 15 2007Oct 17 2007

Publication series

Name2007 IFIP International Conference on Very Large Scale Integration, VLSI-SoC

Other

Other2007 IFIP International Conference on Very Large Scale Integration, VLSI-SoC
CountryUnited States
CityAtlanta, GA
Period10/15/0710/17/07

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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    Malani, P., Mukre, P., & Qiu, Q. (2007). Power optimization for conditional task graphs in DVS enabled multiprocessor systems. In 2007 IFIP International Conference on Very Large Scale Integration, VLSI-SoC (pp. 230-235). [4402503] (2007 IFIP International Conference on Very Large Scale Integration, VLSI-SoC). https://doi.org/10.1109/VLSISOC.2007.4402503