TY - GEN
T1 - Power-aware virtual machine mapping in the data-center-on-a-chip paradigm
AU - Lin, Xue
AU - Xue, Yuankun
AU - Bogdan, Paul
AU - Wang, Yanzhi
AU - Garg, Siddharth
AU - Pedram, Massoud
N1 - Publisher Copyright:
© 2016 IEEE.
PY - 2016/11/22
Y1 - 2016/11/22
N2 - It is projected that hundreds of cores can be integrated into a chip at the sub-20nm technology nodes. However, some challenges exist in the many-core architecture such as maintaining memory coherence, underutilized parallelism, and increased inter-core communication delay. This work proposes the data-center-on-a-chip (DCoC) paradigm employing virtualization technologies commonly used in today's data centers to reduce the overhead of maintaining memory coherence and inter-core communication and improve parallelism. In the DCoC paradigm, user applications with specific resource requirements need to be mapped onto different chips of a data center and different cores of a chip in the form of virtual machines (VMs). By a judicious VM mapping method, the data center performance can be maximized while satisfying the power budget and power density constraints of the chips and the resource requirements of VMs. To tackle the NP-hardness of the VM mapping problem, we propose a two-tier algorithm, which effectively solves the mapping problem with polynomial time complexity.
AB - It is projected that hundreds of cores can be integrated into a chip at the sub-20nm technology nodes. However, some challenges exist in the many-core architecture such as maintaining memory coherence, underutilized parallelism, and increased inter-core communication delay. This work proposes the data-center-on-a-chip (DCoC) paradigm employing virtualization technologies commonly used in today's data centers to reduce the overhead of maintaining memory coherence and inter-core communication and improve parallelism. In the DCoC paradigm, user applications with specific resource requirements need to be mapped onto different chips of a data center and different cores of a chip in the form of virtual machines (VMs). By a judicious VM mapping method, the data center performance can be maximized while satisfying the power budget and power density constraints of the chips and the resource requirements of VMs. To tackle the NP-hardness of the VM mapping problem, we propose a two-tier algorithm, which effectively solves the mapping problem with polynomial time complexity.
UR - http://www.scopus.com/inward/record.url?scp=85006795603&partnerID=8YFLogxK
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U2 - 10.1109/ICCD.2016.7753286
DO - 10.1109/ICCD.2016.7753286
M3 - Conference contribution
AN - SCOPUS:85006795603
T3 - Proceedings of the 34th IEEE International Conference on Computer Design, ICCD 2016
SP - 241
EP - 248
BT - Proceedings of the 34th IEEE International Conference on Computer Design, ICCD 2016
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 34th IEEE International Conference on Computer Design, ICCD 2016
Y2 - 2 October 2016 through 5 October 2016
ER -