Post-processor for data path synthesis using multiport memories

A novel design methodology for data path synthesis using multiport memories is presented which can be applied to scheduled algorithms or to already synthesized data paths as a postprocessor to reduce the design space. Based on simple and clear but powerful principles, the proposed technique not only groups variables to a minimum number of multiport memories depending on their ports and taking into consideration the variables' access requirements, but also minimizes their interconnection hardware (such as buses, multiplexers, and tri-state buffers) to functional units. The system, MAP, supports the synthesis of architecture in both linear topology and random topology for the application-specific design. The minimization problems have been formulated as 0-1 integer linear programming problems. Experiments on benchmarks show very promising results and the CPU time for all the benchmarks is less than 1.4 s.