Phase Directed Compiler Optimizations

Era Jain, Subhajit Roy

Research output: Chapter in Book/Entry/PoemConference contribution

1 Scopus citations


Profile-guided optimizing compilers learn from representative executions of a program to 'tune' transformations so as to benefit frequent paths. However, these optimizations view the whole run of a program in a monolithic manner. It is known that a program execution proceeds in phases - each phase corresponding to an identifiable set of control-flow behaviors. This implies that not all control-flows are hot (i.e. executed with a high frequency) all the times. Hence, if a program can switch among a set of hot paths for guiding the optimizations in the different phases, the optimizations may yield powerful results. We propose an algorithm that optimizes the clones of a function according to the different phase behaviors exhibited by the function, and dispatches its calls to the (potentially) most beneficial clone at runtime. This makes it possible to use profile information at a finer granularity than existing approaches. We start off by identifying critical functions that exhibit a high differential in its control-flow profiles, thereby exhibiting widely varying phase behavior. For these critical functions, we compile specialized clones that are tuned for each distinct phase behavior. Finally, we build a phase predictor that, at run-time, predicts the phase that a yet-to-be-executed function invocation would evoke (when executed), and guides the function invocation to the respective clone of the function. We build the predictor by learning a classifier over features extracted from the state of the program with the distinct phases acting as class labels. We demonstrate our algorithm by building a concrete phase-directed optimizer for register allocation (pdra) within the PBQP-based register allocator in the LLVM compiler infrastructure. We compare our allocator against the base allocator and a profile-guided allocator (pgra) that uses the profile information in a monolithic manner without extracting phase information.

Original languageEnglish (US)
Title of host publicationProceedings - 23rd IEEE International Conference on High Performance Computing, HiPC 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages10
ISBN (Electronic)9781509054114
StatePublished - Feb 1 2017
Externally publishedYes
Event23rd IEEE International Conference on High Performance Computing, HiPC 2016 - Hyderabad, India
Duration: Dec 19 2016Dec 22 2016

Publication series

NameProceedings - 23rd IEEE International Conference on High Performance Computing, HiPC 2016


Conference23rd IEEE International Conference on High Performance Computing, HiPC 2016


  • compiler optimizations
  • machine learning
  • register allocation

ASJC Scopus subject areas

  • Hardware and Architecture


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