Performance Evaluation of Circuit Switched Multistage Interconnection Networks Using a Hold Strategy

The performance evaluation of processor—memory communications for multiprocessor systems using circuit switched interconnection networks with a hold strategy is performed. In addition to the parameters that previous researchers used, we take into account message size and processor processing time which are shown in this paper to have a significant effect on the overall system performance. A closed queueing network model is proposed such that only (n + 2) states are required by the proposed model, in contrast to (n²+ 3n + 4)/2 states needed by previous work, where n is the number of stages of the multistage interconnection network. Moreover, since a closed form solution is obtained, the behavior of a complete cycle of memory access through multistage interconnection networks can be accurately analyzed and various performance bounds can be obtained. Finally, it is pointed out that previous works which did not take message size and processor processing time into account cannot provide accurate information for system performance.