Performance enhancement of CMOS VLSI circuits by transistor recording

Bradley S. Carlson, C. Y.Roger Chen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Scopus citations

Abstract

A method which uses transistor recording for the performance enhancement of CMOS circuits is presented. The proposed technique achieves significant reduction in propagation delays with little effect on layout area. The technique can be coupled with transistor sizing to achieve unbounded improvement in circuit delay, and it can be used to decrease dynamic power dissipation. In particular, excellent results have been achieved when the method is applied to data path circuits.

Original languageEnglish (US)
Title of host publicationProceedings - Design Automation Conference
PublisherIEEE Computer Society
Pages361-366
Number of pages6
ISBN (Print)0897915771
StatePublished - Jan 1 1993
Externally publishedYes
EventProceedings of the 30th ACM/IEEE Design Automation Conference - Dallas, TX, USA
Duration: Jun 14 1993Jun 18 1993

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0146-7123

Other

OtherProceedings of the 30th ACM/IEEE Design Automation Conference
CityDallas, TX, USA
Period6/14/936/18/93

ASJC Scopus subject areas

  • Engineering(all)

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