Performance analysis of single-buffered multistage interconnection networks

Shuo Hsien Hsiao, C. Y.R. Chen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

23 Scopus citations

Abstract

A new model for the performance evaluation of single-buffered multistage interconnection networks (MINs) is proposed. Previous models proposed in solving this problem are either not accurate enough or only applicable to a special case where the switching elements (SEs) are 2 2 crossbars. This new model allows the analysis of a MIN with arbitrary sizes of a a SEs and, through extensive simulations, has been shown to be very accurate. Since only three states are required at each stage of a MIN, this model is efficient computationally.

Original languageEnglish (US)
Title of host publicationProceedings of the 3rd IEEE Symposium on Parallel and Distributed Processing 1991
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages864-867
Number of pages4
ISBN (Electronic)0818623101, 9780818623103
DOIs
StatePublished - Jan 1 1991
Event3rd IEEE Symposium on Parallel and Distributed Processing, PDPS 1991 - Dallas, United States
Duration: Dec 2 1991Dec 5 1991

Publication series

NameProceedings of the 3rd IEEE Symposium on Parallel and Distributed Processing 1991

Conference

Conference3rd IEEE Symposium on Parallel and Distributed Processing, PDPS 1991
CountryUnited States
CityDallas
Period12/2/9112/5/91

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Hardware and Architecture

Cite this

Hsiao, S. H., & Chen, C. Y. R. (1991). Performance analysis of single-buffered multistage interconnection networks. In Proceedings of the 3rd IEEE Symposium on Parallel and Distributed Processing 1991 (pp. 864-867). [218230] (Proceedings of the 3rd IEEE Symposium on Parallel and Distributed Processing 1991). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SPDP.1991.218230