Optimal power switch design methodology for ultra dynamic voltage scaling with a limited number of power rails

Yanzhi Wang, Xue Lin, Massoud Pedram

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

Many burst-mode applications require high performance for brief time periods between extended sections of low performance operation. Digital circuits supporting such burst-mode applications should work in both the near-threshold regime and the super-threshold regime for brief time periods. This work proposes the structure support of fine-grained ultra dynamic voltage scaling (UDVS) from the traditional strong-inversion region to the near-threshold region, with limitations on the number of power rails. The number, type, and size of the power switches are jointly optimized to minimize the overall energy consumption of the UDVS circuit block, meanwhile satisfying the target delay or frequency requirement at each DVS level. The proposed optimization framework properly accounts for the dynamic energy consumption as well as the leakage energy consumption through all the power switches during both the operation time and stand-by time of the circuit block. Experimental results on 22nm Predictive Technology Model demonstrate the effectiveness of the proposed optimization framework.

Original languageEnglish (US)
Title of host publicationGLSVLSI 2014 - Proceedings of the 2014 Great Lakes Symposium on VLSI
PublisherAssociation for Computing Machinery
Pages323-328
Number of pages6
ISBN (Print)9781450328166
DOIs
StatePublished - Jan 1 2014
Event24th Great Lakes Symposium on VLSI, GLSVLSI 2014 - Houston, TX, United States
Duration: May 21 2014May 23 2014

Publication series

NameProceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Other

Other24th Great Lakes Symposium on VLSI, GLSVLSI 2014
CountryUnited States
CityHouston, TX
Period5/21/145/23/14

Keywords

  • near-threshold
  • power switch
  • ultra dynamic voltage scaling (UDVS)

ASJC Scopus subject areas

  • Engineering(all)

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