TY - GEN
T1 - Optimal choice of FinFET devices for energy minimization in deeply-scaled technologies
AU - Abrishami, Mohammad Saeed
AU - Shafaei, Alireza
AU - Wang, Yanzhi
AU - Pedram, Massoud
N1 - Publisher Copyright:
© 2015 IEEE.
PY - 2015/4/13
Y1 - 2015/4/13
N2 - FinFET devices are considered to be the device substitute for bulk CMOS in sub-20nm technology nodes due to the reduced short-channel effects, improved ON/OFF current ratio, and improved voltage scalability. This paper investigates the problem of optimal selection of deeply-scaled FinFET technology to achieve minimum energy consumption for different applications such as sensor applications, smartphones, embedded micro-processors, or server micro-processors, which differ in the required performance and duty ratio. For each application space, different FinFET technologies (with different Vth and gate length biases) are compared in term of minimum energy consumption for both logic circuits and cache memories. A device-circuit-architecture cross-layer framework has been developed to facilitate this technology selection. This optimal technology selection procedure demonstrates up to 11× energy saving compared to poorly selected technologies.
AB - FinFET devices are considered to be the device substitute for bulk CMOS in sub-20nm technology nodes due to the reduced short-channel effects, improved ON/OFF current ratio, and improved voltage scalability. This paper investigates the problem of optimal selection of deeply-scaled FinFET technology to achieve minimum energy consumption for different applications such as sensor applications, smartphones, embedded micro-processors, or server micro-processors, which differ in the required performance and duty ratio. For each application space, different FinFET technologies (with different Vth and gate length biases) are compared in term of minimum energy consumption for both logic circuits and cache memories. A device-circuit-architecture cross-layer framework has been developed to facilitate this technology selection. This optimal technology selection procedure demonstrates up to 11× energy saving compared to poorly selected technologies.
UR - http://www.scopus.com/inward/record.url?scp=84944329465&partnerID=8YFLogxK
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U2 - 10.1109/ISQED.2015.7085431
DO - 10.1109/ISQED.2015.7085431
M3 - Conference contribution
AN - SCOPUS:84944329465
T3 - Proceedings - International Symposium on Quality Electronic Design, ISQED
SP - 234
EP - 238
BT - Proceedings of the 16th International Symposium on Quality Electronic Design, ISQED 2015
PB - IEEE Computer Society
T2 - 16th International Symposium on Quality Electronic Design, ISQED 2015
Y2 - 2 March 2015 through 4 March 2015
ER -