The need for automatic layout and functional cell generation tools is increasing dramatically due to the fast turnaround time desired in the design of integrated circuits. Many optimization algorithms have been proposed in the literature for layout styles which are dual dependent; that is, the optimization for the layout of the n-transistor network of a CMOS complex gate is dependent on the p-transistor network and vice versa. A two-stage linear-time optimization algorithm is presented for dual independent layout styles in this paper. The first stage is based on a tree representation of the complex gate . This tree representation allows complete flexibility in transistor order and takes complete advantage of the concept of delayed binding . The optimization goal is identical to the Euler pathed optimization algorithms presented in  and –. The optimization algorithm is applicable to many VLSI layout styles. In this paper, the algorithm is applied to the M3  layout style and examples of generated layouts are shown. Starting from a switching expression, the proposed algorithm always produces an optimal solution in terms of the number of diffusion breaks, which includes an optimal transistor representation for the switching expression (first stage), and an optimal gate sequence to traverse this transistor circuit (second stage).
|Original language||English (US)|
|Number of pages||13|
|Journal||IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems|
|State||Published - Jun 1991|
ASJC Scopus subject areas
- Computer Graphics and Computer-Aided Design
- Electrical and Electronic Engineering