In many numerical systolic arrays, each processing element in the regular part of the array is itself a linear sytem (called a linear cell). A systematic approach to the design of fault-tolerant systems for such systolic arrays is developed. Most of the proposed systolic arrays for matrix operations, polynomial operations, and digital signal processing can be made fault-tolerant using the authors' procedure. The design procedure preserves the structure of the original (non-fault-tolerant) systolic array, making it easy to incorporate fault tolerance; the faulty units can be identified, which permits reconfiguration if necessary. The design methodology encodes the inputs data at a high level and ensures that the algorithm generates encoded output data; the encoding is tailored to the structure of the systolic array. The encoded input data are passed through the systolic array in ways which will avoid problems with error masking due to failures, resulting in an extremely low overhead for fault tolerance.
|Original language||English (US)|
|Title of host publication||Unknown Host Publication Title|
|Editors||Harold S. Stone|
|Publisher||IEEE Computer Society|
|Number of pages||10|
|State||Published - Dec 1 1986|
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