New layout optimization methodology for CMOS complex gates

C. Y.Roger Chen, Cliff Yungchin Hou

Research output: Chapter in Book/Report/Conference proceedingConference contribution

13 Scopus citations

Abstract

Efficient algorithms for the layout generations of CMOS complex gates are presented. Heuristics which use the concept of delayed binding are introduced. An optimized net list is decided during the layout generation phase, rather than before. Examples showing that this approach can achieve a considerable improvement over previous ones are given.

Original languageEnglish (US)
Title of host publicationIEEE Int Conf on Comput Aided Des ICCAD 88 a Conf for the EE CAD Prof
PublisherIEEE Computer Society
Pages368-371
Number of pages4
ISBN (Print)0818608692
StatePublished - Dec 1 1988

Publication series

NameIEEE Int Conf on Comput Aided Des ICCAD 88 a Conf for the EE CAD Prof

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Chen, C. Y. R., & Hou, C. Y. (1988). New layout optimization methodology for CMOS complex gates. In IEEE Int Conf on Comput Aided Des ICCAD 88 a Conf for the EE CAD Prof (pp. 368-371). (IEEE Int Conf on Comput Aided Des ICCAD 88 a Conf for the EE CAD Prof). IEEE Computer Society.