Efficient algorithms for the layout generations of CMOS complex gates are presented. Heuristics which use the concept of delayed binding are introduced. An optimized net list is decided during the layout generation phase, rather than before. Examples showing that this approach can achieve a considerable improvement over previous ones are given.
|Original language||English (US)|
|Title of host publication||IEEE Int Conf on Comput Aided Des ICCAD 88 a Conf for the EE CAD Prof|
|Publisher||IEEE Computer Society|
|Number of pages||4|
|State||Published - Dec 1 1988|
|Name||IEEE Int Conf on Comput Aided Des ICCAD 88 a Conf for the EE CAD Prof|
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