New algorithm for CMOS gate matrix layout

C. Y.Roger Chen, Cliff Yungchin Hou

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

Efficient algorithms for CMOS gate matrix layouts which have fully utilized the duality between NMOS and PMOS are presented. Improper assumptions made by previous authors are pointed out. Problems which have prevented previous algorithms from reaching a real optimal result are discussed and solved. Significant improvements are achieved over previous algorithms.

Original languageEnglish (US)
Title of host publicationIEEE Int Conf on Comput Aided Des ICCAD 88 a Conf for the EE CAD Prof
PublisherIEEE Computer Society
Pages138-141
Number of pages4
ISBN (Print)0818608692
StatePublished - Dec 1 1988

Publication series

NameIEEE Int Conf on Comput Aided Des ICCAD 88 a Conf for the EE CAD Prof

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Chen, C. Y. R., & Hou, C. Y. (1988). New algorithm for CMOS gate matrix layout. In IEEE Int Conf on Comput Aided Des ICCAD 88 a Conf for the EE CAD Prof (pp. 138-141). (IEEE Int Conf on Comput Aided Des ICCAD 88 a Conf for the EE CAD Prof). IEEE Computer Society.