Efficient algorithms for CMOS gate matrix layouts which have fully utilized the duality between NMOS and PMOS are presented. Improper assumptions made by previous authors are pointed out. Problems which have prevented previous algorithms from reaching a real optimal result are discussed and solved. Significant improvements are achieved over previous algorithms.
|Original language||English (US)|
|Title of host publication||IEEE Int Conf on Comput Aided Des ICCAD 88 a Conf for the EE CAD Prof|
|Publisher||IEEE Computer Society|
|Number of pages||4|
|State||Published - Dec 1 1988|
|Name||IEEE Int Conf on Comput Aided Des ICCAD 88 a Conf for the EE CAD Prof|
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