Abstract
This paper presents performance results for the multi-threaded design and implementation of a parallel pipelined Space-Time Adaptive Processing (STAP) algorithm on parallel computers with Symmetrical Multiple Processor (SMP) nodes. In particular, the paper describes our approach to parallelization and multi-threaded implementation on an Intel Paragon MP system. Our goal is to determine how much more performance can be enhanced using small SMPs on each node of a large parallel computer for such an application. The paper also discusses the process of developing software for such an application on parallel computers when latency and throughput are both considered together and presents their tradeoffs. The results show that not only scalable performance was achieved for individual component tasks of STAP but linear speedups were obtained for the integrated task performance, both for latency as well as throughput.
| Original language | English (US) |
|---|---|
| Title of host publication | Proceedings of the International Parallel Processing Symposium, IPPS |
| Publisher | IEEE Computer Society |
| Pages | 448-452 |
| Number of pages | 5 |
| State | Published - 1999 |
| Event | Proceedings of the 1999 13th International Parallel Processing Symposium and 10th Symposium on Parallel and Distributed Processing - San Juan Duration: Apr 12 1999 → Apr 16 1999 |
Other
| Other | Proceedings of the 1999 13th International Parallel Processing Symposium and 10th Symposium on Parallel and Distributed Processing |
|---|---|
| City | San Juan |
| Period | 4/12/99 → 4/16/99 |
ASJC Scopus subject areas
- Hardware and Architecture