Multi-threaded design and implementation of parallel pipelined STAP on parallel computers with SMP nodes

Wei keng Liao, Alok Choudhary, Donald Weiner, Pramod Kumar Varshney

Research output: Chapter in Book/Report/Conference proceedingChapter

3 Citations (Scopus)

Abstract

This paper presents performance results for the multi-threaded design and implementation of a parallel pipelined Space-Time Adaptive Processing (STAP) algorithm on parallel computers with Symmetrical Multiple Processor (SMP) nodes. In particular, the paper describes our approach to parallelization and multi-threaded implementation on an Intel Paragon MP system. Our goal is to determine how much more performance can be enhanced using small SMPs on each node of a large parallel computer for such an application. The paper also discusses the process of developing software for such an application on parallel computers when latency and throughput are both considered together and presents their tradeoffs. The results show that not only scalable performance was achieved for individual component tasks of STAP but linear speedups were obtained for the integrated task performance, both for latency as well as throughput.

Original languageEnglish (US)
Title of host publicationProceedings of the International Parallel Processing Symposium, IPPS
PublisherIEEE Computer Society
Pages448-452
Number of pages5
StatePublished - 1999
EventProceedings of the 1999 13th International Parallel Processing Symposium and 10th Symposium on Parallel and Distributed Processing - San Juan
Duration: Apr 12 1999Apr 16 1999

Other

OtherProceedings of the 1999 13th International Parallel Processing Symposium and 10th Symposium on Parallel and Distributed Processing
CitySan Juan
Period4/12/994/16/99

Fingerprint

Space time adaptive processing
Throughput

ASJC Scopus subject areas

  • Hardware and Architecture

Cite this

Liao, W. K., Choudhary, A., Weiner, D., & Varshney, P. K. (1999). Multi-threaded design and implementation of parallel pipelined STAP on parallel computers with SMP nodes. In Proceedings of the International Parallel Processing Symposium, IPPS (pp. 448-452). IEEE Computer Society.

Multi-threaded design and implementation of parallel pipelined STAP on parallel computers with SMP nodes. / Liao, Wei keng; Choudhary, Alok; Weiner, Donald; Varshney, Pramod Kumar.

Proceedings of the International Parallel Processing Symposium, IPPS. IEEE Computer Society, 1999. p. 448-452.

Research output: Chapter in Book/Report/Conference proceedingChapter

Liao, WK, Choudhary, A, Weiner, D & Varshney, PK 1999, Multi-threaded design and implementation of parallel pipelined STAP on parallel computers with SMP nodes. in Proceedings of the International Parallel Processing Symposium, IPPS. IEEE Computer Society, pp. 448-452, Proceedings of the 1999 13th International Parallel Processing Symposium and 10th Symposium on Parallel and Distributed Processing, San Juan, 4/12/99.
Liao WK, Choudhary A, Weiner D, Varshney PK. Multi-threaded design and implementation of parallel pipelined STAP on parallel computers with SMP nodes. In Proceedings of the International Parallel Processing Symposium, IPPS. IEEE Computer Society. 1999. p. 448-452
Liao, Wei keng ; Choudhary, Alok ; Weiner, Donald ; Varshney, Pramod Kumar. / Multi-threaded design and implementation of parallel pipelined STAP on parallel computers with SMP nodes. Proceedings of the International Parallel Processing Symposium, IPPS. IEEE Computer Society, 1999. pp. 448-452
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