Modeling and reduction of complex timing constraints in high performance digital circuits

Nagbhushan Veerapaneni, C. Y. Roger Chen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Complex timing constraints that refer to multiple clocks and/or edges are often used in the design of modern high performance processors. Such constraints complicate the design of downstream algorithms such as logic synthesis. The complexity of the overall CAD system can be reduced considerably if we can optimally transform the timing constraints so that they refer only to a single clock and edge. In this paper, we show how to model these multi clock/edge timing constraints and describe algorithms to reduce the number reference clocks/edges. We address the important problems of accurately handling signal transitions, sequential elements, input slope variations and timing overrides, which have not been addressed before.

Original languageEnglish (US)
Title of host publication26th IEEE International Conference on Computer Design 2008, ICCD
Pages544-550
Number of pages7
DOIs
StatePublished - Dec 1 2008
Event26th IEEE International Conference on Computer Design 2008, ICCD - Lake Tahoe, CA, United States
Duration: Oct 12 2008Oct 15 2008

Publication series

Name26th IEEE International Conference on Computer Design 2008, ICCD

Other

Other26th IEEE International Conference on Computer Design 2008, ICCD
CountryUnited States
CityLake Tahoe, CA
Period10/12/0810/15/08

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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