TY - GEN
T1 - Modeling and reduction of complex timing constraints in high performance digital circuits
AU - Veerapaneni, Nagbhushan
AU - Roger Chen, C. Y.
PY - 2008
Y1 - 2008
N2 - Complex timing constraints that refer to multiple clocks and/or edges are often used in the design of modern high performance processors. Such constraints complicate the design of downstream algorithms such as logic synthesis. The complexity of the overall CAD system can be reduced considerably if we can optimally transform the timing constraints so that they refer only to a single clock and edge. In this paper, we show how to model these multi clock/edge timing constraints and describe algorithms to reduce the number reference clocks/edges. We address the important problems of accurately handling signal transitions, sequential elements, input slope variations and timing overrides, which have not been addressed before.
AB - Complex timing constraints that refer to multiple clocks and/or edges are often used in the design of modern high performance processors. Such constraints complicate the design of downstream algorithms such as logic synthesis. The complexity of the overall CAD system can be reduced considerably if we can optimally transform the timing constraints so that they refer only to a single clock and edge. In this paper, we show how to model these multi clock/edge timing constraints and describe algorithms to reduce the number reference clocks/edges. We address the important problems of accurately handling signal transitions, sequential elements, input slope variations and timing overrides, which have not been addressed before.
UR - http://www.scopus.com/inward/record.url?scp=62349140062&partnerID=8YFLogxK
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U2 - 10.1109/ICCD.2008.4751914
DO - 10.1109/ICCD.2008.4751914
M3 - Conference contribution
AN - SCOPUS:62349140062
SN - 9781424426584
T3 - 26th IEEE International Conference on Computer Design 2008, ICCD
SP - 544
EP - 550
BT - 26th IEEE International Conference on Computer Design 2008, ICCD
T2 - 26th IEEE International Conference on Computer Design 2008, ICCD
Y2 - 12 October 2008 through 15 October 2008
ER -