Memristor has emerged as one of the most promising candidates for the fundamental device in the beyond-CMOS era. With their unique advantage on implementing low-power high-speed matrix multiplication, memristors have shown great and vast potentiality in many specific applications. This paper, for the first time, investigates the hardware design of DFT using memristors. Two implementations of DFT using memristors have been presented for effectively trading-off between hardware complexity and computing speed. Simulation results show that as compared to the conventional CMOS-based design, the proposed memristor-based design enables significant reduction in computation latency and improvement in power efficiency with very low inaccuracy. Simulation results show that the proposed memristor-based implementation could reach up to 10X improvement in speed and 109.8X reduction in power efficiency compared to CMOS-based design.