TY - GEN
T1 - Maximizing the performance of NoC-based MPSoCs under total power and power density constraints
AU - Shafaei, Alireza
AU - Wang, Yanzhi
AU - Chen, Lizhong
AU - Chen, Shuang
AU - Pedram, Massoud
N1 - Publisher Copyright:
© 2016 IEEE.
PY - 2016/5/25
Y1 - 2016/5/25
N2 - This paper presents an application mapping problem, which aims to maximize the performance of NoC-based multi-processor system-on-chip (MPSoC) designs without violating the total power and power density budgets of the chip, while maintaining the routability of all communicating cores. The mapping problem also accounts for the fact that, due to process variations, speed and leakage power characteristics of cores and routers may be quite different from one another. The problem is formulated as a mixed-integer, non-linear mathematical program, and solved heuristically by a polynomial-time combinatorial algorithm. The proposed algorithm achieves 34% (31%) on average and 52% (49%) maximum performance improvement under 16nm planar CMOS (7nm FinFET) technology when mapping different applications with different number of tasks to a 64-core processor compared with the baseline algorithms.
AB - This paper presents an application mapping problem, which aims to maximize the performance of NoC-based multi-processor system-on-chip (MPSoC) designs without violating the total power and power density budgets of the chip, while maintaining the routability of all communicating cores. The mapping problem also accounts for the fact that, due to process variations, speed and leakage power characteristics of cores and routers may be quite different from one another. The problem is formulated as a mixed-integer, non-linear mathematical program, and solved heuristically by a polynomial-time combinatorial algorithm. The proposed algorithm achieves 34% (31%) on average and 52% (49%) maximum performance improvement under 16nm planar CMOS (7nm FinFET) technology when mapping different applications with different number of tasks to a 64-core processor compared with the baseline algorithms.
UR - http://www.scopus.com/inward/record.url?scp=84973863990&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84973863990&partnerID=8YFLogxK
U2 - 10.1109/ISQED.2016.7479175
DO - 10.1109/ISQED.2016.7479175
M3 - Conference contribution
AN - SCOPUS:84973863990
T3 - Proceedings - International Symposium on Quality Electronic Design, ISQED
SP - 49
EP - 56
BT - Proceedings of the 17th International Symposium on Quality Electronic Design, ISQED 2016
PB - IEEE Computer Society
T2 - 17th International Symposium on Quality Electronic Design, ISQED 2016
Y2 - 15 March 2016 through 16 March 2016
ER -