TY - GEN
T1 - Low write-energy STT-MRAMs using FinFET-based access transistors
AU - Shafaei, Alireza
AU - Wang, Yanzhi
AU - Pedram, Massoud
N1 - Publisher Copyright:
© 2014 IEEE.
PY - 2014/12/3
Y1 - 2014/12/3
N2 - Spin-Transfer Torque Magnetic RAM (STT-MRAM) technology requires a high current in order to write data into memory cells, which gives rise to large access transistors in conventional MOS-accessed cells. On the other hand, FinFET devices offer higher ON current and denser layout compared with planar CMOS transistors. This paper thus proposes the design of an energy-efficient STT-MRAM cell which utilizes a FinFET access transistor. To assess the performance of the new cell, optimal layout-related parameters of the FinFET access transistor and the MTJ are analytically derived in order to minimize the STT-MRAM cell area. Afterwards, detailed cell- and architecture-level comparisons between FinFET- vs. MOS-accessed STT-MRAMs are performed. According to the comparison results, while the area of the MOS-accessed STT-MRAM increases significantly under 3ns write pulse width (τw), the FinFET-based design can effectively function under τw = 2ns, at the cost of slight increase in the memory area. Hence, the FinFET-accessed STT-MRAM offers denser area and higher energy efficiency compared with the conventional MOS-accessed counterpart.
AB - Spin-Transfer Torque Magnetic RAM (STT-MRAM) technology requires a high current in order to write data into memory cells, which gives rise to large access transistors in conventional MOS-accessed cells. On the other hand, FinFET devices offer higher ON current and denser layout compared with planar CMOS transistors. This paper thus proposes the design of an energy-efficient STT-MRAM cell which utilizes a FinFET access transistor. To assess the performance of the new cell, optimal layout-related parameters of the FinFET access transistor and the MTJ are analytically derived in order to minimize the STT-MRAM cell area. Afterwards, detailed cell- and architecture-level comparisons between FinFET- vs. MOS-accessed STT-MRAMs are performed. According to the comparison results, while the area of the MOS-accessed STT-MRAM increases significantly under 3ns write pulse width (τw), the FinFET-based design can effectively function under τw = 2ns, at the cost of slight increase in the memory area. Hence, the FinFET-accessed STT-MRAM offers denser area and higher energy efficiency compared with the conventional MOS-accessed counterpart.
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U2 - 10.1109/ICCD.2014.6974708
DO - 10.1109/ICCD.2014.6974708
M3 - Conference contribution
AN - SCOPUS:84919667119
T3 - 2014 32nd IEEE International Conference on Computer Design, ICCD 2014
SP - 374
EP - 379
BT - 2014 32nd IEEE International Conference on Computer Design, ICCD 2014
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 32nd IEEE International Conference on Computer Design, ICCD 2014
Y2 - 19 October 2014 through 22 October 2014
ER -