Lookup table based discrete gate sizing for delay minimization with modified elmore delay model

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

Gate sizing is one of the most important techniques for circuit optimization. Over the years, Elmore delay model (EDM) has been the predominant timing model used in gate sizing due to its simplicity. However, EDM is no longer effective in meeting the increasing demand of timing accuracy. In this paper, we propose a new gate delay model, which characterizes the timing information of lookup tables and creates a model which is mathematically similar to EDM, and can be easily incorporated into well-known EDM based gate sizing techniques using Lagrangian Relaxation (LR) with minor modifications. Experimental data show that it can produce even better results than those directly based on lookup tables, while keeping the benefit of the simplicity of EDM.

Original languageEnglish (US)
Title of host publicationGLSVLSI 2015 - 25th 2015 Great Lakes Symposium on VLSI
PublisherAssociation for Computing Machinery
Pages361-366
Number of pages6
Volume20-22-May-2015
ISBN (Electronic)9781450334747
DOIs
StatePublished - May 20 2015
Event25th Great Lakes Symposium on VLSI, GLSVLSI 2015 - Pittsburgh, United States
Duration: May 20 2015May 22 2015

Other

Other25th Great Lakes Symposium on VLSI, GLSVLSI 2015
CountryUnited States
CityPittsburgh
Period5/20/155/22/15

Keywords

  • Delay minimization
  • Discrete gate sizing
  • Elmore delay model
  • Gate model
  • Lookup table

ASJC Scopus subject areas

  • Engineering(all)

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  • Cite this

    Xie, J., & Chen, C. Y. R. (2015). Lookup table based discrete gate sizing for delay minimization with modified elmore delay model. In GLSVLSI 2015 - 25th 2015 Great Lakes Symposium on VLSI (Vol. 20-22-May-2015, pp. 361-366). Association for Computing Machinery. https://doi.org/10.1145/2742060.2742094