We show how hardware implementation descriptions written in Higher Order Logic (HOL) are transformed into VLSI layouts. The intent is to link formally verified designs to physical implementations. Once HOL structural descriptions are transformed to structural descriptions and parameterized cell generators in a VLSI CAD system, the tools associated with the VLSI CAD system can be used such as standard cell libraries, automatic placement and routing, and simulation. The cell generator programs derived from verified HOL descriptions provide a means by which verified and parameterized HOL designs can augment a cell library within a CAD system. The particular VLSI CAD system used here is the GDT system from Mentor Graphics. The GDT system includes a CMOS standard cell library, a macrocell synthesis tool which includes automatic placement and routing, and the Lsim multilevel simulator. GDT uses a structural language called L. HOL structural descriptions are first mapped to L, then layouts corresponding to the L descriptions are created using the standard cell library and the layout generation tools. We illustrate this design process by creating the layout for an 8-bit serial/parallel multiplier which has been verified in HOL.