Leakage power reduction for deeply-scaled FinFET circuits operating in multiple voltage regimes using fine-grained gate-length biasing technique

Ji Li, Qing Xie, Yanzhi Wang, Shahin Nazarian, Massoud Pedram

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Scopus citations

Abstract

With the aggressive downscaling of the process technologies and importance of battery-powered systems, reducing leakage power consumption has become one of the most crucial design challenges for IC designers. This paper presents a device-circuit cross-layer framework to utilize fine-grained gate-length biased FinFETs for circuit leakage power reduction in the near- and super-threshold operation regimes. The impacts of Gate-Length Biasing (GLB) on circuit speed and leakage power are first studied using one of the most advanced technology nodes - a 7nm FinFET technology. Then multiple standard cell libraries using different leakage reduction techniques, such as GLB and Dual-Fj-, are built in multiple operating regimes at this technology node. It is demonstrated that, compared to Dual-Fj-, GLB is a more suitable technique for the advanced 7nm FinFET technology due to its capability of delivering a finer-grained trade-off between the leakage power and circuit speed, not to mention the lower manufacturing cost. The circuit synthesis results of a variety of ISCAS benchmark circuits using the presented GLB 7nm FinFET cell libraries show up to 70% leakage improvement with zero degradation in circuit speed in the near- and super-threshold regimes, respectively, compared to the standard 7nm FinFET cell library.

Original languageEnglish (US)
Title of host publicationProceedings -Design, Automation and Test in Europe, DATE
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1579-1582
Number of pages4
Volume2015-April
ISBN (Print)9783981537048
StatePublished - Apr 22 2015
Externally publishedYes
Event2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015 - Grenoble, France
Duration: Mar 9 2015Mar 13 2015

Other

Other2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015
CountryFrance
CityGrenoble
Period3/9/153/13/15

ASJC Scopus subject areas

  • Engineering(all)

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    Li, J., Xie, Q., Wang, Y., Nazarian, S., & Pedram, M. (2015). Leakage power reduction for deeply-scaled FinFET circuits operating in multiple voltage regimes using fine-grained gate-length biasing technique. In Proceedings -Design, Automation and Test in Europe, DATE (Vol. 2015-April, pp. 1579-1582). [7092643] Institute of Electrical and Electronics Engineers Inc..