Layout characterization and power density analysis for shorted-gate and independent-Gate 7nm FinFET standard cells

Tiansong Cui; Bowen Chen; Yanzhi Wang; Shahin Nazarian; Massoud Pedram

doi:10.1145/2742060.2742093

Layout characterization and power density analysis for shorted-gate and independent-Gate 7nm FinFET standard cells

Tiansong Cui, Bowen Chen, Yanzhi Wang, Shahin Nazarian, Massoud Pedram

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

5 Scopus citations

Abstract

In this paper, a power density analysis is presented for 7nm FinFET technology node based on both shorted-gate (SG) and independentgate (IG) standard cells operating in multiple supply voltage regimes. A Liberty-formatted standard cell library is constructed by selecting the appropriate number of fins for the pull-up and pull-down networks of each logic cell. Next, each cell is characterized by doing SPICE simulations to calculate the propagation delays and output transition times as a function of input transition times and load capacitance values. Finally, the power density of 7nm FinFET technology node is analyzed and compared with the 45 nm CMOS technology node for different circuits. Experimental result shows that the power density of each 7nm FinFET circuit is 3-20 times larger than that of 45nm CMOS circuit under the spacer-defined technology. Experimental result also shows that the back-gate signal enables a better control of power consumption for independentgate FinFETs.

Original language	English (US)
Title of host publication	Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
Publisher	Association for Computing Machinery
Pages	33-38
Number of pages	6
Volume	20-22-May-2015
ISBN (Print)	9781450334747
DOIs	https://doi.org/10.1145/2742060.2742093
State	Published - May 20 2015
Externally published	Yes
Event	25th Great Lakes Symposium on VLSI, GLSVLSI 2015 - Pittsburgh, United States Duration: May 20 2015 → May 22 2015

Other

Other	25th Great Lakes Symposium on VLSI, GLSVLSI 2015
Country	United States
City	Pittsburgh
Period	5/20/15 → 5/22/15

Keywords

FinFET
Independent gate control
Layout
Power density

ASJC Scopus subject areas

Engineering(all)

Access to Document

10.1145/2742060.2742093

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Cite this

Layout characterization and power density analysis for shorted-gate and independent-Gate 7nm FinFET standard cells. / Cui, Tiansong; Chen, Bowen; Wang, Yanzhi; Nazarian, Shahin; Pedram, Massoud.

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI. Vol. 20-22-May-2015 Association for Computing Machinery, 2015. p. 33-38.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Cui, T, Chen, B, Wang, Y, Nazarian, S & Pedram, M 2015, Layout characterization and power density analysis for shorted-gate and independent-Gate 7nm FinFET standard cells. in Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI. vol. 20-22-May-2015, Association for Computing Machinery, pp. 33-38, 25th Great Lakes Symposium on VLSI, GLSVLSI 2015, Pittsburgh, United States, 5/20/15. https://doi.org/10.1145/2742060.2742093

@inproceedings{70ba5451d01b4496a2d872c849727b41,

title = "Layout characterization and power density analysis for shorted-gate and independent-Gate 7nm FinFET standard cells",

abstract = "In this paper, a power density analysis is presented for 7nm FinFET technology node based on both shorted-gate (SG) and independentgate (IG) standard cells operating in multiple supply voltage regimes. A Liberty-formatted standard cell library is constructed by selecting the appropriate number of fins for the pull-up and pull-down networks of each logic cell. Next, each cell is characterized by doing SPICE simulations to calculate the propagation delays and output transition times as a function of input transition times and load capacitance values. Finally, the power density of 7nm FinFET technology node is analyzed and compared with the 45 nm CMOS technology node for different circuits. Experimental result shows that the power density of each 7nm FinFET circuit is 3-20 times larger than that of 45nm CMOS circuit under the spacer-defined technology. Experimental result also shows that the back-gate signal enables a better control of power consumption for independentgate FinFETs.",

keywords = "FinFET, Independent gate control, Layout, Power density",

author = "Tiansong Cui and Bowen Chen and Yanzhi Wang and Shahin Nazarian and Massoud Pedram",

year = "2015",

month = may,

day = "20",

doi = "10.1145/2742060.2742093",

language = "English (US)",

isbn = "9781450334747",

volume = "20-22-May-2015",

pages = "33--38",

booktitle = "Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI",

publisher = "Association for Computing Machinery",

note = "25th Great Lakes Symposium on VLSI, GLSVLSI 2015 ; Conference date: 20-05-2015 Through 22-05-2015",

}

TY - GEN

T1 - Layout characterization and power density analysis for shorted-gate and independent-Gate 7nm FinFET standard cells

AU - Cui, Tiansong

AU - Chen, Bowen

AU - Wang, Yanzhi

AU - Nazarian, Shahin

AU - Pedram, Massoud

PY - 2015/5/20

Y1 - 2015/5/20

N2 - In this paper, a power density analysis is presented for 7nm FinFET technology node based on both shorted-gate (SG) and independentgate (IG) standard cells operating in multiple supply voltage regimes. A Liberty-formatted standard cell library is constructed by selecting the appropriate number of fins for the pull-up and pull-down networks of each logic cell. Next, each cell is characterized by doing SPICE simulations to calculate the propagation delays and output transition times as a function of input transition times and load capacitance values. Finally, the power density of 7nm FinFET technology node is analyzed and compared with the 45 nm CMOS technology node for different circuits. Experimental result shows that the power density of each 7nm FinFET circuit is 3-20 times larger than that of 45nm CMOS circuit under the spacer-defined technology. Experimental result also shows that the back-gate signal enables a better control of power consumption for independentgate FinFETs.

AB - In this paper, a power density analysis is presented for 7nm FinFET technology node based on both shorted-gate (SG) and independentgate (IG) standard cells operating in multiple supply voltage regimes. A Liberty-formatted standard cell library is constructed by selecting the appropriate number of fins for the pull-up and pull-down networks of each logic cell. Next, each cell is characterized by doing SPICE simulations to calculate the propagation delays and output transition times as a function of input transition times and load capacitance values. Finally, the power density of 7nm FinFET technology node is analyzed and compared with the 45 nm CMOS technology node for different circuits. Experimental result shows that the power density of each 7nm FinFET circuit is 3-20 times larger than that of 45nm CMOS circuit under the spacer-defined technology. Experimental result also shows that the back-gate signal enables a better control of power consumption for independentgate FinFETs.

KW - FinFET

KW - Independent gate control

KW - Layout

KW - Power density

UR - http://www.scopus.com/inward/record.url?scp=84955518425&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84955518425&partnerID=8YFLogxK

U2 - 10.1145/2742060.2742093

DO - 10.1145/2742060.2742093

M3 - Conference contribution

AN - SCOPUS:84955518425

SN - 9781450334747

VL - 20-22-May-2015

SP - 33

EP - 38

BT - Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

PB - Association for Computing Machinery

T2 - 25th Great Lakes Symposium on VLSI, GLSVLSI 2015

Y2 - 20 May 2015 through 22 May 2015

ER -