Layout characterization and power density analysis for shorted-gate and independent-Gate 7nm FinFET standard cells

Tiansong Cui, Bowen Chen, Yanzhi Wang, Shahin Nazarian, Massoud Pedram

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Scopus citations

Abstract

In this paper, a power density analysis is presented for 7nm FinFET technology node based on both shorted-gate (SG) and independentgate (IG) standard cells operating in multiple supply voltage regimes. A Liberty-formatted standard cell library is constructed by selecting the appropriate number of fins for the pull-up and pull-down networks of each logic cell. Next, each cell is characterized by doing SPICE simulations to calculate the propagation delays and output transition times as a function of input transition times and load capacitance values. Finally, the power density of 7nm FinFET technology node is analyzed and compared with the 45 nm CMOS technology node for different circuits. Experimental result shows that the power density of each 7nm FinFET circuit is 3-20 times larger than that of 45nm CMOS circuit under the spacer-defined technology. Experimental result also shows that the back-gate signal enables a better control of power consumption for independentgate FinFETs.

Original languageEnglish (US)
Title of host publicationProceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
PublisherAssociation for Computing Machinery
Pages33-38
Number of pages6
Volume20-22-May-2015
ISBN (Print)9781450334747
DOIs
StatePublished - May 20 2015
Externally publishedYes
Event25th Great Lakes Symposium on VLSI, GLSVLSI 2015 - Pittsburgh, United States
Duration: May 20 2015May 22 2015

Other

Other25th Great Lakes Symposium on VLSI, GLSVLSI 2015
CountryUnited States
CityPittsburgh
Period5/20/155/22/15

Keywords

  • FinFET
  • Independent gate control
  • Layout
  • Power density

ASJC Scopus subject areas

  • Engineering(all)

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  • Cite this

    Cui, T., Chen, B., Wang, Y., Nazarian, S., & Pedram, M. (2015). Layout characterization and power density analysis for shorted-gate and independent-Gate 7nm FinFET standard cells. In Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI (Vol. 20-22-May-2015, pp. 33-38). Association for Computing Machinery. https://doi.org/10.1145/2742060.2742093