@inproceedings{70ba5451d01b4496a2d872c849727b41,
title = "Layout characterization and power density analysis for shorted-gate and independent-Gate 7nm FinFET standard cells",
abstract = "In this paper, a power density analysis is presented for 7nm FinFET technology node based on both shorted-gate (SG) and independentgate (IG) standard cells operating in multiple supply voltage regimes. A Liberty-formatted standard cell library is constructed by selecting the appropriate number of fins for the pull-up and pull-down networks of each logic cell. Next, each cell is characterized by doing SPICE simulations to calculate the propagation delays and output transition times as a function of input transition times and load capacitance values. Finally, the power density of 7nm FinFET technology node is analyzed and compared with the 45 nm CMOS technology node for different circuits. Experimental result shows that the power density of each 7nm FinFET circuit is 3-20 times larger than that of 45nm CMOS circuit under the spacer-defined technology. Experimental result also shows that the back-gate signal enables a better control of power consumption for independentgate FinFETs.",
keywords = "FinFET, Independent gate control, Layout, Power density",
author = "Tiansong Cui and Bowen Chen and Yanzhi Wang and Shahin Nazarian and Massoud Pedram",
note = "Funding Information: This research is sponsored in part by grants from the PERFECT program of the Defense Advanced Research Projects Agency. Publisher Copyright: Copyright 2015 ACM.; 25th Great Lakes Symposium on VLSI, GLSVLSI 2015 ; Conference date: 20-05-2015 Through 22-05-2015",
year = "2015",
month = may,
day = "20",
doi = "10.1145/2742060.2742093",
language = "English (US)",
series = "Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI",
publisher = "Association for Computing Machinery",
pages = "33--38",
booktitle = "GLSVLSI 2015 - 25th 2015 Great Lakes Symposium on VLSI",
}