Joint sizing and adaptive independent gate control for FinFET circuits operating in multiple voltage regimes using the logical effort method

Xue Lin, Yanzhi Wang, Massoud Pedram

Research output: Chapter in Book/Report/Conference proceedingConference contribution

26 Scopus citations

Abstract

FinFET has been proposed as an alternative for bulk CMOS in current and future technology nodes due to more effective channel control, reduced random dopant fluctuation, high ON/OFF current ratio, lower energy consumption, etc. Key characteristics of FinFET operating in the sub/near-threshold region are very different from those in the strong-inversion region. This paper first introduces an analytical transregional FinFET model with high accuracy in both sub- and near-threshold regimes. Next, the paper extends the well-known and widely-adopted logical effort delay calculation and optimization method to FinFET circuits operating in multiple voltage (sub/near/super-threshold) regimes. More specifically, a joint optimization of gate sizing and adaptive independent gate control is presented and solved in order to minimize the delay of FinFET circuits operating in multiple voltage regimes. Experimental results on a 32nm Predictive Technology Model for FinFET demonstrate the effectiveness of the proposed logical effort-based delay optimization framework.

Original languageEnglish (US)
Title of host publication2013 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2013 - Digest of Technical Papers
Pages444-449
Number of pages6
DOIs
StatePublished - Dec 1 2013
Event2013 32nd IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2013 - San Jose, CA, United States
Duration: Nov 18 2013Nov 21 2013

Publication series

NameIEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
ISSN (Print)1092-3152

Other

Other2013 32nd IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2013
CountryUnited States
CitySan Jose, CA
Period11/18/1311/21/13

Keywords

  • FinFET
  • delay optimization
  • independent gate control
  • logical effort
  • sub/near-threshold

ASJC Scopus subject areas

  • Software
  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design

Fingerprint Dive into the research topics of 'Joint sizing and adaptive independent gate control for FinFET circuits operating in multiple voltage regimes using the logical effort method'. Together they form a unique fingerprint.

  • Cite this

    Lin, X., Wang, Y., & Pedram, M. (2013). Joint sizing and adaptive independent gate control for FinFET circuits operating in multiple voltage regimes using the logical effort method. In 2013 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2013 - Digest of Technical Papers (pp. 444-449). [6691155] (IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD). https://doi.org/10.1109/ICCAD.2013.6691155