Multiport memories provide an effective way for efficiently implementing large VLSI chips and are actually being used in the design of many recent high speed RISC and SuperScalar processors. With the use of multiport memories, interconnect minimization (such as buses, multiplexers and tri-state buffers) has become more difficult. This is due to the fact that in order to establish a connection from a register to a functional unit, we need to properly assign registers to the ports of memory in different control steps in order to save interconnection. In this paper a 0-1 integer linear programming (ILP) model is presented which performs functional unit and connection allocation tasks simultaneously to get better results assuming that registers have already been grouped into multiport memories. Experiments on benchmarks show very promising results.