Interconnection minimization in multiport memories based data path synthesis

Imtiaz Ahmad, C. Y. Roger Chen

Research output: Chapter in Book/Report/Conference proceedingConference contribution


Multiport memories provide an effective way for efficiently implementing large VLSI chips and are actually being used in the design of many recent high speed RISC and SuperScalar processors. With the use of multiport memories, interconnect minimization (such as buses, multiplexers and tri-state buffers) has become more difficult. This is due to the fact that in order to establish a connection from a register to a functional unit, we need to properly assign registers to the ports of memory in different control steps in order to save interconnection. In this paper a 0-1 integer linear programming (ILP) model is presented which performs functional unit and connection allocation tasks simultaneously to get better results assuming that registers have already been grouped into multiport memories. Experiments on benchmarks show very promising results.

Original languageEnglish (US)
Title of host publication1992 Proceedings of the 35th Midwest Symposium on Circuits and Systems
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages4
ISBN (Electronic)0780305108
StatePublished - 1992
Event35th Midwest Symposium on Circuits and Systems, MWSCAS 1992 - Washington, United States
Duration: Aug 9 1992Aug 12 1992

Publication series

NameMidwest Symposium on Circuits and Systems
ISSN (Print)1548-3746


Conference35th Midwest Symposium on Circuits and Systems, MWSCAS 1992
Country/TerritoryUnited States

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


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