TY - GEN
T1 - Interconnection minimization in multiport memories based data path synthesis
AU - Ahmad, Imtiaz
AU - Roger Chen, C. Y.
N1 - Publisher Copyright:
© 1992 IEEE.
PY - 1992
Y1 - 1992
N2 - Multiport memories provide an effective way for efficiently implementing large VLSI chips and are actually being used in the design of many recent high speed RISC and SuperScalar processors. With the use of multiport memories, interconnect minimization (such as buses, multiplexers and tri-state buffers) has become more difficult. This is due to the fact that in order to establish a connection from a register to a functional unit, we need to properly assign registers to the ports of memory in different control steps in order to save interconnection. In this paper a 0-1 integer linear programming (ILP) model is presented which performs functional unit and connection allocation tasks simultaneously to get better results assuming that registers have already been grouped into multiport memories. Experiments on benchmarks show very promising results.
AB - Multiport memories provide an effective way for efficiently implementing large VLSI chips and are actually being used in the design of many recent high speed RISC and SuperScalar processors. With the use of multiport memories, interconnect minimization (such as buses, multiplexers and tri-state buffers) has become more difficult. This is due to the fact that in order to establish a connection from a register to a functional unit, we need to properly assign registers to the ports of memory in different control steps in order to save interconnection. In this paper a 0-1 integer linear programming (ILP) model is presented which performs functional unit and connection allocation tasks simultaneously to get better results assuming that registers have already been grouped into multiport memories. Experiments on benchmarks show very promising results.
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U2 - 10.1109/MWSCAS.1992.271118
DO - 10.1109/MWSCAS.1992.271118
M3 - Conference contribution
AN - SCOPUS:85065700229
T3 - Midwest Symposium on Circuits and Systems
SP - 1032
EP - 1035
BT - 1992 Proceedings of the 35th Midwest Symposium on Circuits and Systems
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 35th Midwest Symposium on Circuits and Systems, MWSCAS 1992
Y2 - 9 August 1992 through 12 August 1992
ER -