Heuristic for data path synthesis using multiport memories

Imtiaz Ahmad, Chien Yi Roger Chen

Research output: Chapter in Book/Entry/PoemConference contribution


Recently there is a trend for the designer to group registers into register files for efficiently implementing large VLSI chips. Multiport memories provide an effective way for such an implementation. Interconnection minimization (such as multiplexers and Tri-state buffers) has become more difficult with the use of multiport memories. In this paper, a heuristic is presented which performs functional units and connection Allocation task simulatneously to get better results for application specific designs assuming that registers have already been grouped to multiport memories. Experiments on benchmarks show very promising results.

Original languageEnglish (US)
Title of host publicationProc Second Great Lakes Symp VLSI
PublisherIEEE Computer Society
Number of pages8
StatePublished - 1991
EventProceedings of the Second Great Lakes Symposium on VLSI - Kalamazoo, MI, USA
Duration: Feb 28 1992Feb 29 1992


OtherProceedings of the Second Great Lakes Symposium on VLSI
CityKalamazoo, MI, USA

ASJC Scopus subject areas

  • General Engineering


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