Abstract
Recently there is a trend for the designer to group registers into register files for efficiently implementing large VLSI chips. Multiport memories provide an effective way for such an implementation. Interconnection minimization (such as multiplexers and Tri-state buffers) has become more difficult with the use of multiport memories. In this paper, a heuristic is presented which performs functional units and connection Allocation task simulatneously to get better results for application specific designs assuming that registers have already been grouped to multiport memories. Experiments on benchmarks show very promising results.
Original language | English (US) |
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Title of host publication | Proc Second Great Lakes Symp VLSI |
Publisher | IEEE Computer Society |
Pages | 44-51 |
Number of pages | 8 |
State | Published - 1991 |
Event | Proceedings of the Second Great Lakes Symposium on VLSI - Kalamazoo, MI, USA Duration: Feb 28 1992 → Feb 29 1992 |
Other
Other | Proceedings of the Second Great Lakes Symposium on VLSI |
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City | Kalamazoo, MI, USA |
Period | 2/28/92 → 2/29/92 |
ASJC Scopus subject areas
- General Engineering