Recently there is a trend for the designer to group registers into register files for efficiently implementing large VLSI chips. Multiport memories provide an effective way for such an implementation and are actually being used in the design of many recent high-speed RISC and SuperScalar processors. An efficient design methodology for grouping variables into multiport memories is presented, which is an essential step for multiport memories based data path synthesis. The proposed technique not only groups variables into a minimum number of multiport memory modules, but also simultaneously minimizes the number of registers in each memory module. The minimization problem has been formulated as a 0–1 integer linear programming problem. Experiments on benchmarks show very promising results.
|Original language||English (US)|
|Number of pages||4|
|Journal||IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing|
|State||Published - Sep 1992|
ASJC Scopus subject areas
- Signal Processing
- Electrical and Electronic Engineering