Gridless multi-layer area router

Naresh Kumar Sehgal; C. Y.Roger Chen; John M. Acken

Gridless multi-layer area router

Naresh Kumar Sehgal, C. Y.Roger Chen, John M. Acken

Research output: Contribution to journal › Conference Article › peer-review

Abstract

This paper presents an algorithm to route multiple nets for VLSI layout synthesis in the presence of irregular rectilinear obstacles. The proposed routing algorithms are to be used when layout is nearly finished. Any incremental routing for performance needs to be done by using the very limited space between existing layout cells or by routing directly over the cells. Each net has multiple pins, which are located either on the boundary or anywhere inside the layout region. The proposed algorithm is very systematic and easy to implement. It does not require any net sequencing, and through extensive experiments on real circuits has been shown to always produce near optimal solutions.

Original language	English (US)
Pages (from-to)	158-161
Number of pages	4
Journal	Proceedings of the IEEE Great Lakes Symposium on VLSI
State	Published - 1994
Externally published	Yes
Event	Proceedings of the 4th Great Lakes Symposium on VLSI - Notre Dame, IN, USA Duration: Mar 4 1994 → Mar 5 1994

ASJC Scopus subject areas

Electrical and Electronic Engineering

Cite this

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title = "Gridless multi-layer area router",

abstract = "This paper presents an algorithm to route multiple nets for VLSI layout synthesis in the presence of irregular rectilinear obstacles. The proposed routing algorithms are to be used when layout is nearly finished. Any incremental routing for performance needs to be done by using the very limited space between existing layout cells or by routing directly over the cells. Each net has multiple pins, which are located either on the boundary or anywhere inside the layout region. The proposed algorithm is very systematic and easy to implement. It does not require any net sequencing, and through extensive experiments on real circuits has been shown to always produce near optimal solutions.",

author = "Sehgal, {Naresh Kumar} and Chen, {C. Y.Roger} and Acken, {John M.}",

year = "1994",

language = "English (US)",

pages = "158--161",

journal = "Proceedings of the IEEE Great Lakes Symposium on VLSI",

issn = "1066-1395",

publisher = "IEEE Computer Society",

note = "Proceedings of the 4th Great Lakes Symposium on VLSI ; Conference date: 04-03-1994 Through 05-03-1994",

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T1 - Gridless multi-layer area router

AU - Sehgal, Naresh Kumar

AU - Chen, C. Y.Roger

AU - Acken, John M.

PY - 1994

Y1 - 1994

N2 - This paper presents an algorithm to route multiple nets for VLSI layout synthesis in the presence of irregular rectilinear obstacles. The proposed routing algorithms are to be used when layout is nearly finished. Any incremental routing for performance needs to be done by using the very limited space between existing layout cells or by routing directly over the cells. Each net has multiple pins, which are located either on the boundary or anywhere inside the layout region. The proposed algorithm is very systematic and easy to implement. It does not require any net sequencing, and through extensive experiments on real circuits has been shown to always produce near optimal solutions.

AB - This paper presents an algorithm to route multiple nets for VLSI layout synthesis in the presence of irregular rectilinear obstacles. The proposed routing algorithms are to be used when layout is nearly finished. Any incremental routing for performance needs to be done by using the very limited space between existing layout cells or by routing directly over the cells. Each net has multiple pins, which are located either on the boundary or anywhere inside the layout region. The proposed algorithm is very systematic and easy to implement. It does not require any net sequencing, and through extensive experiments on real circuits has been shown to always produce near optimal solutions.

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M3 - Conference Article

AN - SCOPUS:0028747292

SN - 1066-1395

SP - 158

EP - 161

JO - Proceedings of the IEEE Great Lakes Symposium on VLSI

JF - Proceedings of the IEEE Great Lakes Symposium on VLSI

T2 - Proceedings of the 4th Great Lakes Symposium on VLSI

Y2 - 4 March 1994 through 5 March 1994

ER -

Gridless multi-layer area router

Abstract

ASJC Scopus subject areas

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