Gridless multi-layer area router

Naresh Kumar Sehgal, C. Y.Roger Chen, John M. Acken

Research output: Contribution to journalConference articlepeer-review

Abstract

This paper presents an algorithm to route multiple nets for VLSI layout synthesis in the presence of irregular rectilinear obstacles. The proposed routing algorithms are to be used when layout is nearly finished. Any incremental routing for performance needs to be done by using the very limited space between existing layout cells or by routing directly over the cells. Each net has multiple pins, which are located either on the boundary or anywhere inside the layout region. The proposed algorithm is very systematic and easy to implement. It does not require any net sequencing, and through extensive experiments on real circuits has been shown to always produce near optimal solutions.

Original languageEnglish (US)
Pages (from-to)158-161
Number of pages4
JournalProceedings of the IEEE Great Lakes Symposium on VLSI
StatePublished - Dec 1 1994
Externally publishedYes
EventProceedings of the 4th Great Lakes Symposium on VLSI - Notre Dame, IN, USA
Duration: Mar 4 1994Mar 5 1994

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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