From Logic to Symbolic Layout for Gate Matrix

Uminder Singh, C. Y. Roger Chen

Research output: Contribution to journalArticle

2 Scopus citations

Abstract

Gate matrix is a style which allows random logic layout to be performed in a regular manner. An algorithm is introduced which uses logic equations to determine a gate sequence and a set of nets which optimize the layout area. Using logic equations allows the reordering of transistors in a completely general manner. Previous works which use dynamic net lists and the concept of delayed binding perform only a small subset of the reordering possible with the proposed algorithm. Our algorithm uses a net-list-independent technique to determine the gate sequence. An optimized net list is created after the gate sequence is known. The algorithm has a time complexity of O(E log E) for a design with E logic equations. The experimental results show a considerable reduction in layout area.

Original languageEnglish (US)
Pages (from-to)216-227
Number of pages12
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume11
Issue number2
DOIs
StatePublished - Feb 1992

ASJC Scopus subject areas

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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