FinCACTI: Architectural analysis and modeling of caches with deeply-scaled FinFET devices

Alireza Shafaei; Yanzhi Wang; Xue Lin; Massoud Pedram

doi:10.1109/ISVLSI.2014.94

FinCACTI: Architectural analysis and modeling of caches with deeply-scaled FinFET devices

Alireza Shafaei, Yanzhi Wang, Xue Lin, Massoud Pedram

Research output: Chapter in Book/Entry/Poem › Conference contribution

64 Scopus citations

Abstract

This paper presents FinCACTI, a cache modeling tool based on CACTI which also supports deeply-scaled FinFET devices as well as more robust SRAM cells. In particular, FinFET devices optimized using advanced device simulators for 7nm process serve as the case study of the paper. Based on this 7nm FinFET process, characteristics of 6T and 8T SRAMs are calculated, and comparison results show that under the same stability requirements the 8T cell has smaller area and leakage power. SRAM and technological parameters of the 7nm FinFET are then incorporated into FinCACTI. According to architecture-level simulations, the 8T SRAM is suggested as the choice of memory cell for 7nm FinFET. Moreover, a 4MB cache in 7nm FinFET compared with 22nm (32nm) CMOS under same access latencies achieves 5× (9×) and 11× (24×) reduction in read energy and area, respectively.

Original language	English (US)
Title of host publication	Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
Publisher	IEEE Computer Society
Pages	290-295
Number of pages	6
ISBN (Electronic)	9781479937639
DOIs	https://doi.org/10.1109/ISVLSI.2014.94
State	Published - Sep 18 2014
Externally published	Yes
Event	2014 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2014 - Tampa, United States Duration: Jul 9 2014 → Jul 11 2014

Other

Other	2014 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2014
Country/Territory	United States
City	Tampa
Period	7/9/14 → 7/11/14

Keywords

CACTI
Cache Modeling
FinFET devices

ASJC Scopus subject areas

Hardware and Architecture
Control and Systems Engineering
Electrical and Electronic Engineering

Access to Document

10.1109/ISVLSI.2014.94

Cite this

Shafaei, A, Wang, Y, Lin, X & Pedram, M 2014, FinCACTI: Architectural analysis and modeling of caches with deeply-scaled FinFET devices. in Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI., 6903378, IEEE Computer Society, pp. 290-295, 2014 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2014, Tampa, United States, 7/9/14. https://doi.org/10.1109/ISVLSI.2014.94

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title = "FinCACTI: Architectural analysis and modeling of caches with deeply-scaled FinFET devices",

abstract = "This paper presents FinCACTI, a cache modeling tool based on CACTI which also supports deeply-scaled FinFET devices as well as more robust SRAM cells. In particular, FinFET devices optimized using advanced device simulators for 7nm process serve as the case study of the paper. Based on this 7nm FinFET process, characteristics of 6T and 8T SRAMs are calculated, and comparison results show that under the same stability requirements the 8T cell has smaller area and leakage power. SRAM and technological parameters of the 7nm FinFET are then incorporated into FinCACTI. According to architecture-level simulations, the 8T SRAM is suggested as the choice of memory cell for 7nm FinFET. Moreover, a 4MB cache in 7nm FinFET compared with 22nm (32nm) CMOS under same access latencies achieves 5× (9×) and 11× (24×) reduction in read energy and area, respectively.",

keywords = "CACTI, Cache Modeling, FinFET devices",

author = "Alireza Shafaei and Yanzhi Wang and Xue Lin and Massoud Pedram",

note = "Publisher Copyright: {\textcopyright} 2014 IEEE.; 2014 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2014 ; Conference date: 09-07-2014 Through 11-07-2014",

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doi = "10.1109/ISVLSI.2014.94",

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AU - Shafaei, Alireza

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AU - Pedram, Massoud

PY - 2014/9/18

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N2 - This paper presents FinCACTI, a cache modeling tool based on CACTI which also supports deeply-scaled FinFET devices as well as more robust SRAM cells. In particular, FinFET devices optimized using advanced device simulators for 7nm process serve as the case study of the paper. Based on this 7nm FinFET process, characteristics of 6T and 8T SRAMs are calculated, and comparison results show that under the same stability requirements the 8T cell has smaller area and leakage power. SRAM and technological parameters of the 7nm FinFET are then incorporated into FinCACTI. According to architecture-level simulations, the 8T SRAM is suggested as the choice of memory cell for 7nm FinFET. Moreover, a 4MB cache in 7nm FinFET compared with 22nm (32nm) CMOS under same access latencies achieves 5× (9×) and 11× (24×) reduction in read energy and area, respectively.

AB - This paper presents FinCACTI, a cache modeling tool based on CACTI which also supports deeply-scaled FinFET devices as well as more robust SRAM cells. In particular, FinFET devices optimized using advanced device simulators for 7nm process serve as the case study of the paper. Based on this 7nm FinFET process, characteristics of 6T and 8T SRAMs are calculated, and comparison results show that under the same stability requirements the 8T cell has smaller area and leakage power. SRAM and technological parameters of the 7nm FinFET are then incorporated into FinCACTI. According to architecture-level simulations, the 8T SRAM is suggested as the choice of memory cell for 7nm FinFET. Moreover, a 4MB cache in 7nm FinFET compared with 22nm (32nm) CMOS under same access latencies achieves 5× (9×) and 11× (24×) reduction in read energy and area, respectively.

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KW - Cache Modeling

KW - FinFET devices

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FinCACTI: Architectural analysis and modeling of caches with deeply-scaled FinFET devices

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