Abstract
This article describes various techniques for fault tolerance that can be applied to systolic array architectures. The approach of algorithm-based fault tolerance is shown to be the natural one for such systems.
Original language | English (US) |
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Pages | 65-75 |
Number of pages | 11 |
Volume | 20 |
No | 7 |
Specialist publication | Computer |
DOIs | |
State | Published - Jul 1987 |
Externally published | Yes |
ASJC Scopus subject areas
- General Computer Science